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P4080 CoreNet Platform Cache (CPC) configured as SRAM has a high access time standard deviation

Question asked by Steven Verhoff on Jan 24, 2018
Latest reply on Jan 31, 2018 by alexander.yakovlev

I have configured the CPC as SRAM on the P4080, and the access time appears to have a high standard deviation. In other words, the time to access the SRAM is inconsistent. I have compared this with accessing NOR flash on the board, and accessing the SRAM has a higher standard deviation. I am using a XES Xpedite 5470 board. I have tried enabling and disabling the L1 and L2 caches without any success. All my tests have been running a u-boot stand alone program on bare metal, no operating system. This way I can easily control enabling and disabling the caches, as well as the external interrupts. However, doing all of this has not yielded the timing results I expected from accessing the SRAM. I am looking for consistent timing results.