I'm working on an IMX6SL design. I have a power management question. After powering down in u-boot I see that PMIC_ON_REQ goes down almost immediately after writing to the TOP bit. The ONOFF pad remains high. While powering down there is no other input to the SNVS sub-system other than setting bits 0, 5 and 6 of SNVS_LPCR.
However, some 10.4ms later, PMIC_STBY_REQ goes high. This brings the PMIC (PF0100) into standby mode. I am able to prevent the PMIC from outputting supply voltages in this mode, that is not the issue. The problem is that it consumes too much power in standby mode, and disables standby from being used properly in other places of the design.
So: How do I prevent PMIC_STBY_REQ from being set high during a power-off event?
Should I touch VSTBY or STBY_COUNT in CCM_CLPCR?