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How to improve the low throughput on the WEIM CS0 Address Bus

Question asked by Deepak Kukreja on Jan 22, 2018
Latest reply on Jan 22, 2018 by igorpadykov

Hi,

For our prototypes we have used i.MX51 with an FPGA.

The FPGA is interfaced to the iMX as a memory mapped peripheral, and is interfaced using the External Memory Interface on the WEIM CS0.
The EIM is configured to work in 16 bit Address-Data Multiplexed Asynchronous mode.
The issue that we are facing is that we are not able to get the desired data rate on the EIM Bus.

Reason seems to be the large gap (approx 150 to 180 nano-seconds) between two successive writes to the memory bus.
While the write access is being made the CS assertion time is approx 240 nano-seconds for 32 WEIM clock cycles @133MHz.

We are not able to understand the root cause of this issue, we have used different configuration values for the WEIM configuration registers
without much improvement.

WEIM Configuration register settings are below:
0x00010039 , //CSxGCR1
0x00000002 , //CSxGCR2
0x20475230 , //CSxRCR1
0x00000000 , //CSxRCR2
0x609C0E98 , //CSxWCR1
0x00000000 , //CSxWCR2

Our prototypes have cleared the beta field trials and we are ready to go in production, but the issue we are facing is that we are unable to increase the data rate substantially.
At the current data rate we will not be able to meet higher throughput specifications and address only a fraction of the market need.

Can someone please tell me how can I bring down the time in between of two successive Chip Selects.

Does synchronous mode provide a better data rate?

I know that iMX51 is an old part but we are already upgrading our subsystems and are considering iMX7 device, but we need to increase the throughput on this
bus.

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