According to QorIQ LS1043A Reference Manual, Rev. 3, 02/2017, Table 4-14., the CGA_PLL2_SPD bit in RCW should be set to 1 for PLL2 frequencies from 800MHz to 1000.1 MHz):
but the RCW for LS1043A in SDK does not care about this bit and leave it to 0 even for 1000MHz PLL2. For example here:
I have verified RCW binaries generated from the above descriptions and there is really CGA_PLL2_SPD set to 0.
What do you recommend? Follow the Reference Manual or follow the SDK for 1000MHz PLL2 settings (for our custom board RCW)?