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TSA HDLC in MPC8309

Question asked by Akhilesh Chidare on Jan 16, 2018
Latest reply on Jan 17, 2018 by Akhilesh Chidare

We are using MPC8309 for our router application. In which I configured UCC5 in HDLC (NMSI) mode for V.35(serial) interface which is working fine. Now when I am configuring UCC5 for Time division Multipex(TDM) in Time slot Assigner(TSA) mode, I am facing issue in transmitting the packets out of UCC. Receive is working fine.
I am configuring UCC5 and TDMB in TSA mode,
We are working on (E1 ) TDM interface. we have configured for 32 timeslots.
we have provided 2.048MHz clock and 8KHz Sync for both Rx and Tx.

MPC_TCLK = TDM_RCLK     2.048 MHz
MPC_RCLK = TDM_RCLK  

MPC_TSYNC = TDM_RSYNC   8KHz
MPC_RSYNC = TDM_RSYNC  

MPC_RDATA = TDM_RDATA
TDM_TDATA = MPC_TDATA

with this my receive hdlc is working fine. i am able to receive packets and my counters are also incrementing.
but my transmit data is not functioning. i am unable to see HDLC frames on this. i have monitored this on the oscilloscope.

when we set the CRTx (common rx and tx pins) in SI mode register, the we can see HDLC frames on the TXD pin.
but we want to operate on independent rx and tx clock and syncs. this is must for our application.

 

following are the configurations.

 

1) Configured siram.tx & siram.rx Bank 0
TX : dump_siram: SI TxRAM dump - bank offset=0
siram entry 0 to 30 : 0x003C & last entry 31 : 0x003D
RX : dump_siram: SI1 RxRAM dump - bank offset=0
siram entry 0 to 30 : 0x003C & last entry 31 : 0x003D
2) Configured SI1's sibmr1
si1.sibmr1 = 0x0000;
3) QUICC's CMX registers
cmxucr1 = 0x60000000 here I tried another value also 0x40000000
cmxsi1cr_l = 0x6000600
cmxsi1cr_h = 0x0
cmxsi1syr = 0x0
4) After configuring UCC5 in fast mode I am enabling TDMB by configuring si1's siglmr1_h register.
siglmr1_h = 0x2

TDMB's TX Clock is TDM2_TCK (CLK6) & RX Clock is TDM2_RCK (CLK5), for this I configured SICR2 register.
dump SICR_2 = 0x00800e00

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