I was wondering whether anyone could explain the rationale for powering the i.MX6 NVCC_ENET rail with the VGEN6_3V3 (PF0100 VGEN6 LDO) instead of the GEN_3V3 (PF0100 SW2 switched) supply on the SABRE boards. We have the MCIMX6Q-SDB, but I believe all recent versions of the SABRE boards are set up this way. I realize that the SH24 jumper allows ETH_3V3 to be separated from VGEN6_3V3, but I don't see any rules in the datasheet, reference manual, or HDG that preclude using the general 3V3 rail for the NVCC_ENET bank. SW2 does not appear to be close to its rated load on the SABRE; I also don't see any good reason to change the voltage of the bank. The only thing that comes to mind is some sequencing issue: SW2 is #5 in the PF0100 startup sequence, and VGEN6 is #8. What am I missing? Can anyone with intimate knowledge of the SABRE designs explain why NVCC_ENET was not connected to GEN_3V3 along with the other 3V3 NVCC rails?
We are having issues with permanent damage to IO pads on the GEN_3V3 rail in our design, which is based heavily on the SABRE (a formal support case is being set in motion through our distributor). One of the very few differences in our design is that the NVCC_ENET is powered by GEN_3V3 along with everything else. On the off chance that another adopter has run into issues with this, or that someone from the SABRE design team is watching this forum, I thought I'd try my luck.
Thanks in advance,