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LPC2294/01 CAN Rx Failure on Data Overload

Question asked by Michael Hul on Jan 15, 2018
Latest reply on Feb 6, 2018 by CarlosCasillas
Branched to a new discussion

First some background....

I'm running an LPC2294/01 with a CAN bus connection to an external PC running CAN simulation software (Vector CANalyzer/CANoe). The problem I've been encountering is as follows: when the unit (LPC2294) is off and the simulator is running (ie. attempting to transmit data to the unit), the unacknowledged messages are buffered into a queue of some fixed size (I do not have control over this behavior). When the unit is then powered on and initializes its CAN controller (SJA1000), the simulator then barfs that queued data onto the bus as fast as the controller will ACK it, before continuing with the fixed-period real-time data. This often leads to a Data Overrun fault since the software does not expect this sudden dump at the beginning and therefore does not sample the receive registers fast enough. After this occurs, the CAN controller no longer signals any incoming/received data to the software (CANGSR RBS bit stays 0), despite continuing to ACK those incoming messages. After much searching I found the Errata document for this microcontroller (ES_LPC229x/01) which explained the issue as follows:




In a Data Overrun condition, the CAN controller is locked from further message reception.


1. Recovering from this situation is only possible with a soft reset to the CAN controller.




Taking the advice, I updated the software to reset the CAN controller upon detection of the Data Overrun (based on the CANGSR DOS bit). This helped significantly, but it still was not a 100% fix. The behavior described in the Errata where the CAN Rx buffer is locked from receiving any new data still happens occasionally with no indication of data overrun in any of the controller registers. It's not clear to me if something else is going on. So, this becomes a two part question:


1) Is it possible for the scenario described in the Errata (ES_LPC229x/01 section 3.2), to occur even if no data overrun is signaled by the corresponding register bits (either CANGSR DOS, or CANICR DOI)?


2) If the answer above is 'Yes', is there another work around besides increasing the sampling rate? The acceptance filter is already configured to pass through only valid data. The problem occurs when multiple instances of these valid IDs are received much faster than their expected period.


Any ideas are appreciated.