our FPGA is connected to the LS1021 processor via PCIe lane.
The system software identifies the PCIe device (FPGA) and writes the absolute memory addresses of a mapped memory area to the BAR-Registers of the FPGA.
The software can read/write from/to BAR registers without problems.
The FPGA begins writing data from the FPGA to the LS1021 memory (TLP MWr).
We can see the written data in the LS1021 memory but the FPGA device will not receive completion TLPs (TLP-Cpl).
In the next step the FPGA requests data from the LS1021 root complex (TLP MRd) but no completion with data TLPs are received (TLP CplD).
In parallel the FPGA initiates an interrupt. This works fine.
Question: What’s going wrong?
Hint: We are using same FPGA on X86 platform. This works fine.