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i.MX6solo bt656 4 D1 input

Question asked by llinguo cui on Jan 10, 2018
Latest reply on Jan 10, 2018 by igorpadykov

Hi  Qiang,

      We are using i.MX6solo  for  SDTV  surround view solution .The input video decode chip is tvp5158,our BSP version is3.14.52.

   For  single channel input mode ,we can get the interlaced video data .We set the register 

CSI_ACT_FRM_SIZE=(720-1)x(576-1)CSI_SENS_FRM_SIZE=(720-1)x(625-1);and set  csi_param.clk_mode =3;

But ,in the four channels mode ,we set the register 

CSI_ACT_FRM_SIZE=(720-1)x(576-1)CSI_SENS_FRM_SIZE=(720-1)x(625-1);and set  csi_param.clk_mode =0;

After we get the video data ,we found that we lost some lines for each channel .

In the document of tvp5158,we read that in the four channels line interleaved Mode ,all the 4channels D1 data is  rearranged,they call it super frame .The  super frame size  is 720x2502(576*4+2blanking ).I updated tow pictures about the super frame .

This time ,we set CSI_ACT_FRM_SIZE , CSI_SENS_FRM_SIZE for 720x2502(576*4+2blanking ).The kernel come out the warning log:

[   29.542328] imx-ipuv3 2400000.ipu: IC output size(2496) cannot exceed 1024

[   29.549507] imx-ipuv3 2400000.ipu: failed to calculate prpenc height scaling coefficients

 

Can The i.MX6solo soc support the super frame size 720x2502?How I need to set the CSI_ACT_FRM_SIZE , CSI_SENS_FRM_SIZE for the super frame size ?

 

By the way ,in the 4channels D1input mode .the pixel clk is 108Mhz,we need set this parameter in some IPU register ?

 

In  the dts file ,I set these items :

 compatible = "tvp5158";
 reg = <0x58>;
pwn-gpios =` <&gpio1 2 0>;

 pinctrl-names = "default";

csi_id = <0>;
pinctrl-0 = <&pinctrl_ipu1_2>;
 clocks = <&clks IMX6QDL_CLK_CKO>;
 clock-names = "csi_mclk";
 mclk = <24000000>;
 mclk_source = <0>;
 About the clock items ,the item 'mclk' need to be set 108000000?

Actually ,I don't understand the meaning about the clock items ,can you give some document to read ?

Thank you very much !

 

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