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QCVS / Validation of DDR

Question asked by Radek Raichel on Jan 9, 2018
Latest reply on Feb 25, 2018 by Yiping Wang

Hi community,

 

I have a question to validation of DDR. With CodeWarrior for Power Architecture (10.5.1) and activated license for DDR Validation we get a nonsense results. For example following results we got for a test of skews on different memory lanes:


 

Our configuration:

- T2081

- 64-bit DDR3L + 8-bit ECC

- 933MHz CLK 

 

With CodeWarrior for ARMv8 and Layerscape LS1046A ist the validation of DRAM ok.

 

Any ideas, what's wrong?

 

Thank you very much!

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