I have a question to validation of DDR. With CodeWarrior for Power Architecture (10.5.1) and activated license for DDR Validation we get a nonsense results. For example following results we got for a test of skews on different memory lanes:
- 64-bit DDR3L + 8-bit ECC
- 933MHz CLK
With CodeWarrior for ARMv8 and Layerscape LS1046A ist the validation of DRAM ok.
Any ideas, what's wrong?
Thank you very much!