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eQADC, CFIFO SW trigger is not working

Question asked by Mohamed Hedi BASLY on Jan 9, 2018
Latest reply on Jan 12, 2018 by David Tosenovjan



on my project i got a ReloadTask launched by EMIOS timer each 121us to trigger SLOW, FAST and Calibration conversion ISR.


for each Opération i got the following configuration :

SLOW conversion :

- CFIFO1 configured to generate DMA requests

- RFIFO3 Configured to generate DMA requests

FAST conversion :

- CFIFO4 configured to generate DMA requests

- RFIFO2 Configured to generate DMA requests

Calibration conversion :

- CFIFO5 configured to generate DMA requests

- RFIFO0 Configured to generate DMA requests


on init function for my ADC module I execute the previous configuration and i initialize the ADC0 and ADC1 internal registers using CFIFO0 in order to write the correct configuration to enable both ADCs.


The idea is the write commands to the CFIFO with DMA, then once the Commands are ready on the RFIFO another DMA channel will transfer the data to system memory and launch and ISR after end of transfer to save the data in buffers to be used by upper layer.


The Calibration is only triggered once by the RelaodTask to update the GCC and OCC internal registers of both ADCs in order to improve the measurement. a CalibDone flag is used to indicate the calibration is done the the acquisition sequence is ready to start.

in the ReloadTask, if the CalibDone Flag is raised then feed DMA commands for both FAST and SLOW conversion by starting DMA transfert and SW triggering the corresponding CFIFO.


The mechanism is working perfectly, but i want to update this by making the Calib conversion ISR a periodic event with 12ms period to keep updating the GCC and OCC to have a better accurate measurement. So i added a counter that count 12ms in the ReloadTask, once the period is reached a CalibUpdate flag is raised to execute calibration ISR, the DMA transfert is done on the ReloadTask, but the trigger is executed after finishing the FAST conversion, the problem is that the ISR does not strat at all.


before i start the DMA transfer to the CFIFO5 i remarked that the CFIFO Counter RFCTR is equal to 4 which means the CFIFO is already FULL so i can't write more commands. is there an explanation to that. 

I used the CFIFO5 for the first time Calibration and it works fine.

I debugged the situation and i found out the the FIFO Counter is not decremented after executing the first command burst. the calibration commands are 4 commands to read the VRH and VRL for each ADC.


Any proposition are appreciated. Thanks in advance. ☺