Hello,
In case it can be helpful, the following procedure has worked for us:
1. Holdoff release (see function holdoff_release )
2. Set boot address (see function set_second_boot_addr )
3. Execute sev instruction (ex. asm("sev"))
Below the assembler code :
#define CONFIG_SYS_IMMR 0x01000000
#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
#define DCFG_CCSR_BRR 0x0E4
#define DCFG_CCSR_SCRATCHRW1 0x200
.globl holdoff_release
holdoff_release:
@ Clear and Get the correct CPU number
movw r1, #0xf01
and r1, r1, #0xff
@ Get DCFG base address
movw r4, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff)
movt r4, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16)
@ Release on target CPU
ldr r2, [r4, #DCFG_CCSR_BRR]
mov r6, #1
lsl r6, r6, r1 @ 32 bytes per CPU
rev r6, r6
orr r2, r2, r6
str r2, [r4, #DCFG_CCSR_BRR]
.globl set_second_boot_addr
set_second_boot_addr:
@ Get DCFG base address
movw r4, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff)
movt r4, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16)
@ Set secondary boot address
@ldr r6, r0
mov r6, r0
rev r6, r6
str r6, [r4, #DCFG_CCSR_SCRATCHRW1]
@ Return written
mov r0, r6
