AnsweredAssumed Answered

DDR3 configuration for imx6q processor

Question asked by Sanket Parekh on Jan 4, 2018
Latest reply on Jan 10, 2018 by Ritesh Patel

Hi.

 

Greetings.

 

We are working on imx6q processor, our custom board have one DDR3 of 512MB. So i have configured DDR for imx6q processor from I.MX6DQSDL DDR3 Script Aid V0.10.xlsx. When i load the u-boot with configured DDR on our custom board, u-boot image will not flash properly.

 

iMX6Q: MCIMX6Q6AVT08AD

DDR3: MT41K256M16TW-107 AAT:P

DDR type is DDR3   
Data width: 16, bank num: 8  
Row size: 15, col size: 10  
Chip select CSD0 is used   
Density per chip select: 512MB

 

We are generation DDR3 configuration from "I.MX6DQSDL DDR3 Script Aid V0.10.xlsx" file and using "DDR_Stress_Tester_V1.0.2" tool we are configuring and calibrating the DDR3 on custom board.

 

Is there any register value mismatch for DQS?

Is there any sequence we are missing?

 

So please give me some solution for the same.

Configuration file are present in attachments.

 

LOG:

============================================  
        DDR Stress Test (2.6.0)   
        Build: Aug  1 2017, 17:33:25  
        NXP Semiconductors.  
============================================  
 
============================================  
        Chip ID  
CHIP ID = i.MX6 Dual/Quad (0x63)  
Internal Revision = TO1.5  
============================================  
 
============================================  
        Boot Configuration  
SRC_SBMR1(0x020d8004) = 0x00005878  
SRC_SBMR2(0x020d801c) = 0x3a000001  
============================================  
 
ARM Clock set to 800MHz  
 
============================================  
        DDR configuration  
BOOT_CFG3[5-4]: 0x00, Single DDR channel.  
DDR type is DDR3   
Data width: 16, bank num: 8  
Row size: 15, col size: 10  
Chip select CSD0 is used   
Density per chip select: 512MB   
============================================  
 
Current Temperature: 31  
============================================  
 
DDR Freq: 396 MHz   
 
ddr_mr1=0x00000004  
Start write leveling calibration...  
running Write level HW calibration  
Write leveling calibration completed, update the following registers in your initialization script  
    MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x001F001F  
    MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x001F001F  
Write DQS delay result:  
   Write DQS0 delay: 31/256 CK  
   Write DQS1 delay: 31/256 CK  
 
Starting DQS gating calibration  
. HC_DEL=0x00000000    result[00]=0x00000011  
. HC_DEL=0x00000001    result[01]=0x00000011  
. HC_DEL=0x00000002    result[02]=0x00000011  
. HC_DEL=0x00000003    result[03]=0x00000011  
. HC_DEL=0x00000004    result[04]=0x00000011  
. HC_DEL=0x00000005    result[05]=0x00000011  
. HC_DEL=0x00000006    result[06]=0x00000011  
. HC_DEL=0x00000007    result[07]=0x00000011  
. HC_DEL=0x00000008    result[08]=0x00000011  
. HC_DEL=0x00000009    result[09]=0x00000011  
. HC_DEL=0x0000000A    result[0A]=0x00000011  
. HC_DEL=0x0000000B    result[0B]=0x00000011  
. HC_DEL=0x0000000C    result[0C]=0x00000011  
. HC_DEL=0x0000000D    result[0D]=0x00000011  
ERROR FOUND, we can't get suitable value !!!!  
dram test fails for all values.   
 
Error: failed during ddr calibration

 

Thank you.

Sanket

Attachments

Outcomes