Hi all,
We are working on a device connected to ecspi3 interface of imx7d sabre sd board. We tried to read the chip version from the module but the transaction always returns zero. After debugging the we found that chip select(NSS) should be held down for 16 clock cycles in order to read data from the module but in imx7 the chip select line becomes high after transferring 8 bits. Attached the image of SPI transaction expected by our device,
To avoid this we configured chip select as gpio and tried to control it manually from our driver code. But with this method we are not receiving any clock from the master. Here is our device tree entry.
&ecspi3 {
fsl,spi-num-chipselects = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs>;
pinctrl-0 = <&pinctrl_ecspi3>;
/*cs-gpios = <&gpio6 22 GPIO_ACTIVE_HIGH>;*/ NOTE: Commented the cs-gpios entry
/*cs-gpios = <0>;*/ NOTE: Tried this entry also without this entry
status = "okay";
spidev0: spi@0 {
compatible = "rfm95";
reg = <0>;
spi-max-frequency = <4000000>;
interrupt-parent = <&gpio2>;
interrupts = <11 1>;
cs-gpio = <&gpio6 22 GPIO_ACTIVE_HIGH>; NOTE: Used this gpio for Chip select from our driver.
intr-gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
rst-gpio = <&gpio2 10 GPIO_ACTIVE_HIGH>;
enable-gpio = <&gpio2 0 GPIO_ACTIVE_HIGH>;
};
}
RESULT:
On doing this the chip select line toggles, but there is not clock from the SCLK line.
So,
1. Is there anything we missed to configure chip select as gpio?
2.Is there any patch available for 4.9.11 kernel to configure chip select as gpio to control it in iMX7D?
3. Is there any working patch available to avoid SPI controller(spi-imx.c) toggling chip select after transferring 8 bits?
Thanks,
Koil Arul Raj S
