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EIM timing definition

Question asked by Kazuma Sasaki on Dec 25, 2017
Latest reply on Dec 27, 2017 by Kazuma Sasaki

Hi Community,

 

We are developing custom board with i.MX6D. However, we can not clearly understand specification of EIM timing parameters.

 

From IMX6DQAEC REV.5

 

Linux BSP implementation:

  AXI_CLK_ROOT = 198MHz = PLL2 PFD2 396MHz / 2

  ACLK_EIM_SLOW_CLK_ROOT = 99MHz = AXI_CLK_ROOT / 2

 

Questions:

Q1.

The datasheet is described that "t means clock period from axi_clk frequency".

In above case, should we use AXI_CLK_ROOT(198MHz) for "clock period for t"?

I suppose we should use ACLK_EIM_SLOW_CLK_ROOT(99MHz) instead of AXI_CLK_ROOT(198MHz). Is it right?

 

Q2.

From IMX6SDLAEC REV.8

 

EIM timing definitions are different between i.MX6S/DL and i.MX6D/Q/DP/QP such as above figures.

I suppose i.MX6S and i.MX6D are using same EIM controller. but, why timing definitions are different as above?

 

Best Regards,

Kazuma Sasaki.

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