EIM timing definition

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EIM timing definition

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Kazuma_Sasaki
Senior Contributor I

Hi Community,

We are developing custom board with i.MX6D. However, we can not clearly understand specification of EIM timing parameters.

From IMX6DQAEC REV.5

pastedImage_6.png

pastedImage_7.png

Linux BSP implementation:

  AXI_CLK_ROOT = 198MHz = PLL2 PFD2 396MHz / 2

  ACLK_EIM_SLOW_CLK_ROOT = 99MHz = AXI_CLK_ROOT / 2

Questions:

Q1.

The datasheet is described that "t means clock period from axi_clk frequency".

In above case, should we use AXI_CLK_ROOT(198MHz) for "clock period for t"?

I suppose we should use ACLK_EIM_SLOW_CLK_ROOT(99MHz) instead of AXI_CLK_ROOT(198MHz). Is it right?

Q2.

From IMX6SDLAEC REV.8

pastedImage_8.png

EIM timing definitions are different between i.MX6S/DL and i.MX6D/Q/DP/QP such as above figures.

I suppose i.MX6S and i.MX6D are using same EIM controller. but, why timing definitions are different as above?

Best Regards,

Kazuma Sasaki.

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igorpadykov
NXP Employee
NXP Employee

Hi Kazuma 

1.> I suppose we should use ACLK_EIM_SLOW_CLK_ROOT(99MHz) instead of AXI_CLK_ROOT(198MHz). Is it right?

right

2. >why timing definitions are different as above?

timings are the same, first makes more sense as according to

EIM EIM_CSnRCR1 definition CSA is EIM clock cycles, so "unit" is given

as combination "t"&CSA.

Best regards
igor
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igorpadykov
NXP Employee
NXP Employee

Hi Kazuma 

1.> I suppose we should use ACLK_EIM_SLOW_CLK_ROOT(99MHz) instead of AXI_CLK_ROOT(198MHz). Is it right?

right

2. >why timing definitions are different as above?

timings are the same, first makes more sense as according to

EIM EIM_CSnRCR1 definition CSA is EIM clock cycles, so "unit" is given

as combination "t"&CSA.

Best regards
igor
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

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Kazuma_Sasaki
Senior Contributor I

Hi igor,

I appreciate your support. Let me confirm regarding Q2.

<Conditions>

(1) CSA = 1 cycle

(2) ACLK_EIM_SLOW_CLK_ROOT = 99MHz = 10.1 ns time per cycle

(3) Timing definition

From IMX6DQAEC REV.5

pastedImage_6.png

pastedImage_7.png

From IMX6SDLAEC REV.8

pastedImage_8.png

<Calculation>

In case of i.MX6D : WE31 MAX = 3.5 - CSA x t = 3.5 - 10.1 = -6.6ns

In case of i.MX6S : WE31 MAX = 3 - CSA = 3 - 10.1 = -7.1ns

<Question>

Is the above calculation correct? If correct, why timings are same in above case?

Best Regards,

Kazuma Sasaki.

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igorpadykov
NXP Employee
NXP Employee

Hi Kazuma 

I think calculations are correct.

Where did you see that timings are same ?

Best regards
igor

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Kazuma_Sasaki
Senior Contributor I

Hi igor,

I might not have understood that your first answer correctly.

You told me that "timings are the same" at your first answer on this thread.

I am worried about typo for EIM timing which described on datasheet.

Best Regards,

Kazuma Sasaki.

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igorpadykov
NXP Employee
NXP Employee

Hi Kazuma 

 

if you mean WE31, they are not the same.

 

Best regards
igor

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Kazuma_Sasaki
Senior Contributor I

Hi Igor,

I got it. thank you so much for your support.

Best Regards,

Kazuma Sasaki.

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