i.MX6 IPU di0_vsync_ext

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i.MX6 IPU di0_vsync_ext

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sugiyamatoshihi
Contributor V

Hi, 

I have a question about di0_vsync_ext in DI0 General Register.

Which pin provide external VSYNC to DIx? 

It seems PIN01 is capable but I cannot find how to change input and output.

Best Regards,

Sugiyama

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Yuri
NXP Employee
NXP Employee

Hello,

 

   from Table 37-6 (IPU1 External Signals) of i.MX6 D/Q RM:

 IPU1_DI1_PIN01 may serve as IPU1_DI1_EXT_VSYNC on  EIM_DA15 in ALT1 mode.
According to Table 4-2 (Muxing Options) EIM_DA15 is controlled with help of 

IOMUXC_SW_MUX_CTL_PAD_EIM_AD15 register. Bit SION may be used to force input

path.

Have a great day,

Yuri

 

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sugiyamatoshihi
Contributor V

Hi, Yuri,

Thank you the answer.

I believe SION use like daisy chain.

I think EIM_DA15 PAD with IPU1_DI1_PIN01 is output , if SION set enabled, external VSYNC and PIN01 output are conflicted.

What do you think?

Best Regards,

Sugiyama

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sugiyamatoshihi
Contributor V

Hi, Yuri,

I checked di0_vsync_ext of IPU2_DI0.  It seems di0_vsync_ext bit didn't affect Vsync. 

If I changed the value of di0_run_valuem1_3 in IPU2_DI0_SW_GEN0_3 for Vsync, this value change affect both di0_vsync_ext=0 and 1. I suppose External to IPU means Vsync come from another module, but DI register seems to be related.

What is change di0_vsync_ext bit?

 

Best Regards,

Sugiyama

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