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LPC43S57: SDRAM performance

Question asked by Johan Borkhuis on Dec 20, 2017
Latest reply on Dec 28, 2017 by Johan Borkhuis

I am working with the LPC43S57 (running at 204 MHz) and am evaluating the external SDRAM performance. I am using the MT48LC4M32B2 128Mb*32 SDRAM from Micron.

To test the performance I use the gpdma_speed application from LPCOpen 3.01, using GDMA to make sure the application does not influence the transfer speed.

I modified the application to test different memory areas, including internal memory. I write 1 MB of data in chunks of 12 kB to the same 12 kB buffer, so it will fit in internal memory.

 

The results I see are a bit disappointing to me. Transfer from internal to internal memory is 80 MW/s (W = 32 bit), this is quite good. But transfer from external SDRAM to SDRAM is max 17 MW/s. How can I improve the speed of the SDRAM, to be closer to the internal speed? I would like to be able to execute from external SDRAM, but for that the speed should be better.

 

All measured results of 1MB transfer:

  • Internal to internal: 80 MW/s
  • External to external: 17 MW/s
  • Internal to external: 50 MW/s
  • External to internal: 26 MW/s

 

The configuration i use is:

static const IP_EMC_DYN_CONFIG_T MT48LC4M32_config =
{
    /// Row refresh period.
    EMC_NANOSECOND(64000000 / 4096),
    /// Clock?
    0x01,
    /// tRP: Precharge Command Period. (ns)
    EMC_NANOSECOND(18),
    /// tRAS: Active to Precharge Command Period. (ns)
    EMC_NANOSECOND(42),
    /// tSREX: Self Refresh Exit Time. (ns), same as tXSR
    EMC_NANOSECOND(67),
    /// tAPR: Last Data Out to Active Time. (ns) ??
    EMC_CLOCK(0x01),
    /// tDAL: Data In to Active Command Time. (ns)
    EMC_CLOCK(0x04),
    /// tWR: Write Recovery Time. (ns)
    EMC_NANOSECOND(12),
    /// tRC: Active to Active Command Period. (ns)
    EMC_NANOSECOND(60),
    /// tRFC: Auto-refresh Period. (ns)
    EMC_NANOSECOND(60),
    /// tXSR: Exit Self Refresh. (ns)
    EMC_NANOSECOND(67),
    /// tRRD: Active Bank A to Active Bank B Time. (ns)
    EMC_NANOSECOND(12),
    /// tMRD Load Mode register command to Active command. (clocks)
    EMC_CLOCK(0x02),
    /// Device Configuration array.
    {
        {
            /// For the Xenon board, EMC_DYCS0 is used.
            EMC_ADDRESS_DYCS0,
            /// RAS value.
            2,
            /// Mode Register value.
            EMC_DYN_MODE_WBMODE_PROGRAMMED | EMC_DYN_MODE_OPMODE_STANDARD |
            EMC_DYN_MODE_CAS_2 | EMC_DYN_MODE_BURST_TYPE_SEQUENTIAL |
            EMC_DYN_MODE_BURST_LEN_4,
            /// Dynamic Configuration value.
            EMC_DYN_CONFIG_DATA_BUS_32 |
            EMC_DYN_CONFIG_4Mx32_4BANKS_12ROWS_8COLS | EMC_DYN_CONFIG_MD_SDRAM
        },
        {0, 0, 0, 0},
        {0, 0, 0, 0},
        {0, 0, 0, 0}
    }
};

 

Regards,

Johan Borkhuis

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