I checked the i.MX6DQ datasheet but I couldn't understand the note#4 which attached to the uSDHC bus timing table.
I think hold time is specified and clear as tIH>1.5ns.
Why note#4 added?
note#4: "To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns."
It seems redundant spec for the uSDHC IP or something or obsolete.
Futhermore clock is obviously not input but output always.
I compared to the LS1020A datasheet. There is no such notes.
Can anyone explain me?