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How to enable EIM CS1 in u-boot of i.mx6?

Question asked by jun kim on Dec 12, 2017
Latest reply on Dec 13, 2017 by igorpadykov

hello everyone

 

My system is

bootloader: u-boot200908

kernel : L3.0.35 LTIB

I want use EIM CS1 (8bit mode) in u-boot level...

What I applied:  

/u-boot/board/freescale/mx6q_sabresd/mx6q_sabresd.c

iomux_v3_cfg_t   weim_pads[] = {

  MX6DL_PAD_EIM_OE__WEIM_WEIM_OE,

  MX6DL_PAD_EIM_RW__WEIM_WEIM_RW,

  MX6DL_PAD_EIM_CS0__WEIM_WEIM_CS_0,

  MX6DL_PAD_EIM_CS1__WEIM_WEIM_CS_1,

  MX6DL_PAD_DISP0_DAT8__GPIO_4_29,

  MX6DL_PAD_EIM_LBA__WEIM_WEIM_LBA,

  MX6DL_PAD_EIM_BCLK__WEIM_WEIM_BCLK,

 

 MX6DL_PAD_CSI0_DAT12__WEIM_WEIM_D_8,

MX6DL_PAD_CSI0_DAT13__WEIM_WEIM_D_9,

MX6DL_PAD_CSI0_DAT14__WEIM_WEIM_D_10,

MX6DL_PAD_CSI0_DAT15__WEIM_WEIM_D_11,

MX6DL_PAD_CSI0_DAT16__WEIM_WEIM_D_12,

MX6DL_PAD_CSI0_DAT17__WEIM_WEIM_D_13,

MX6DL_PAD_CSI0_DAT18__WEIM_WEIM_D_14,

MX6DL_PAD_CSI0_DAT19__WEIM_WEIM_D_15,

...

};

 

void setup_eim(void)

{

     u32 reg = 0;

    mxc_iomux_v3_setup_multiple_pads(weim_pads,ARRAY_SIZE(weim_pads));

    reg = readl(IOMUXC_BASE_ADDR + 0x4);   // GPR1 register  CS0/CS1 enable

    reg &= ~0x07ffffff;

    reg |= 0x1b;

    writel(reg, IOMUXC_BASE_ADDR + 0x4);

writel(0x00851081,(WEIM_BASE_ADDR + 0x18));    //CS1GCR1

writel(0x00000001,(WEIM_BASE_ADDR + 0x18 + 0x4));    //CS1GCR2

writel(0x1C022000,(WEIM_BASE_ADDR + 0x18 + 0x8));    //CS1RCR1

writel(0x0000C000,(WEIM_BASE_ADDR + 0x18 + 0xC));    //CS1RCR2

writel(0x1404A38E,(WEIM_BASE_ADDR + 0x18 + 0x10));    //CS1WCR

}

/u-boot/board/freescale/mx6q_sabresd/lowlevel_init.S

ldr r0, CCM_BASE_ADDR_W

....

ldr r1, =0xFFC

str r1, [r0, #CLKCTL_CCGR6]

...

/u-boot/board/freescale/mx6q_sabresd/flash_header.S

none .

 

EIM CS1 does not work after applying the above. 

HOW do i get EIM CS1 to work????

 

Pleas help me....

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