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imx6q ddr stress test fail

Question asked by jiu jin hong on Dec 11, 2017
Latest reply on Dec 12, 2017 by jiu jin hong

============================================
        DDR Stress Test (2.6.0)
        Build: Aug  1 2017, 17:33:25
        NXP Semiconductors.
============================================
        Chip ID
CHIP ID = i.MX6 Dual/Quad (0x63)
Internal Revision = TO1.5
============================================

 

============================================
        Boot Configuration
SRC_SBMR1(0x020d8004) = 0x00005860
SRC_SBMR2(0x020d801c) = 0x31000001
============================================

 

ARM Clock set to 800MHz

 

============================================
        DDR configuration
BOOT_CFG3[5-4]: 0x00, Single DDR channel.
DDR type is DDR3
Data width: 64, bank num: 8
Row size: 15, col size: 10
Chip select CSD0 is used
Density per chip select: 2048MB
============================================

 

Current Temperature: 51
============================================

 

DDR Freq: 528 MHz

 

ddr_mr1=0x00000000
Start write leveling calibration...
running Write level HW calibration
Write leveling calibration completed, update the following registers in your initialization script
    MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x001F0019
    MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x001F0023
    MMDC_MPWLDECTRL0 ch1 (0x021b480c) = 0x0018001F
    MMDC_MPWLDECTRL1 ch1 (0x021b4810) = 0x0006001F
Write DQS delay result:
   Write DQS0 delay: 25/256 CK
   Write DQS1 delay: 31/256 CK
   Write DQS2 delay: 35/256 CK
   Write DQS3 delay: 31/256 CK
   Write DQS4 delay: 31/256 CK
   Write DQS5 delay: 24/256 CK
   Write DQS6 delay: 31/256 CK
   Write DQS7 delay: 6/256 CK

 

Starting DQS gating calibration
. HC_DEL=0x00000000    result[00]=0x11111111
. HC_DEL=0x00000001    result[01]=0x01100111
. HC_DEL=0x00000002    result[02]=0x00100001
. HC_DEL=0x00000003    result[03]=0x00000000
. HC_DEL=0x00000004    result[04]=0x01000000
. HC_DEL=0x00000005    result[05]=0x11111111
. HC_DEL=0x00000006    result[06]=0x11111111
. HC_DEL=0x00000007    result[07]=0x11111111
. HC_DEL=0x00000008    result[08]=0x11111111
. HC_DEL=0x00000009    result[09]=0x11111111
. HC_DEL=0x0000000A    result[0A]=0x11111111
. HC_DEL=0x0000000B    result[0B]=0x11111111
. HC_DEL=0x0000000C    result[0C]=0x11111111
. HC_DEL=0x0000000D    result[0D]=0x11111111
DQS HC delay value low1 = 0x01020203, high1=0x04040404
DQS HC delay value low2 = 0x01020301, high2=0x04030404

 

loop ABS offset to get HW_DG_LOW
. ABS_OFFSET=0x00000000    result[00]=0x01000111
. ABS_OFFSET=0x00000004    result[01]=0x01000110
. ABS_OFFSET=0x00000008    result[02]=0x01000111
. ABS_OFFSET=0x0000000C    result[03]=0x11011110
. ABS_OFFSET=0x00000010    result[04]=0x01000110
. ABS_OFFSET=0x00000014    result[05]=0x01000110
. ABS_OFFSET=0x00000018    result[06]=0x11011110
. ABS_OFFSET=0x0000001C    result[07]=0x01000110
. ABS_OFFSET=0x00000020    result[08]=0x01000110
. ABS_OFFSET=0x00000024    result[09]=0x01000110
. ABS_OFFSET=0x00000028    result[0A]=0x11001110
. ABS_OFFSET=0x0000002C    result[0B]=0x11000110
. ABS_OFFSET=0x00000030    result[0C]=0x00000110
. ABS_OFFSET=0x00000034    result[0D]=0x00000110
. ABS_OFFSET=0x00000038    result[0E]=0x10001110
. ABS_OFFSET=0x0000003C    result[0F]=0x10011110
. ABS_OFFSET=0x00000040    result[10]=0x00000110
. ABS_OFFSET=0x00000044    result[11]=0x00000110
. ABS_OFFSET=0x00000048    result[12]=0x00010110
. ABS_OFFSET=0x0000004C    result[13]=0x00000110
. ABS_OFFSET=0x00000050    result[14]=0x00000110
. ABS_OFFSET=0x00000054    result[15]=0x00000110
. ABS_OFFSET=0x00000058    result[16]=0x00000110
. ABS_OFFSET=0x0000005C    result[17]=0x00010010
. ABS_OFFSET=0x00000060    result[18]=0x00000010
. ABS_OFFSET=0x00000064    result[19]=0x00000010
. ABS_OFFSET=0x00000068    result[1A]=0x00000010
. ABS_OFFSET=0x0000006C    result[1B]=0x00000010
. ABS_OFFSET=0x00000070    result[1C]=0x00000000
. ABS_OFFSET=0x00000074    result[1D]=0x00000000
. ABS_OFFSET=0x00000078    result[1E]=0x00000000
. ABS_OFFSET=0x0000007C    result[1F]=0x00000000

 

loop ABS offset to get HW_DG_HIGH
. ABS_OFFSET=0x00000000    result[00]=0x00000000
. ABS_OFFSET=0x00000004    result[01]=0x00000000
. ABS_OFFSET=0x00000008    result[02]=0x00000000
. ABS_OFFSET=0x0000000C    result[03]=0x00000000
. ABS_OFFSET=0x00000010    result[04]=0x00000000
. ABS_OFFSET=0x00000014    result[05]=0x00000000
. ABS_OFFSET=0x00000018    result[06]=0x00000000
. ABS_OFFSET=0x0000001C    result[07]=0x00000000
. ABS_OFFSET=0x00000020    result[08]=0x10000100
. ABS_OFFSET=0x00000024    result[09]=0x10000100
. ABS_OFFSET=0x00000028    result[0A]=0x10000100
. ABS_OFFSET=0x0000002C    result[0B]=0x10101100
. ABS_OFFSET=0x00000030    result[0C]=0x10101100
. ABS_OFFSET=0x00000034    result[0D]=0x10101110
. ABS_OFFSET=0x00000038    result[0E]=0x10101110
. ABS_OFFSET=0x0000003C    result[0F]=0x10111110
. ABS_OFFSET=0x00000040    result[10]=0x10111110
. ABS_OFFSET=0x00000044    result[11]=0x10111110
. ABS_OFFSET=0x00000048    result[12]=0x10111111
. ABS_OFFSET=0x0000004C    result[13]=0x10111111
. ABS_OFFSET=0x00000050    result[14]=0x10111111
. ABS_OFFSET=0x00000054    result[15]=0x10111111
. ABS_OFFSET=0x00000058    result[16]=0x10111111
. ABS_OFFSET=0x0000005C    result[17]=0x10111111
. ABS_OFFSET=0x00000060    result[18]=0x11111111
. ABS_OFFSET=0x00000064    result[19]=0x11111111
. ABS_OFFSET=0x00000068    result[1A]=0x11111111
. ABS_OFFSET=0x0000006C    result[1B]=0x11111111
. ABS_OFFSET=0x00000070    result[1C]=0x11111111
. ABS_OFFSET=0x00000074    result[1D]=0x11111111
. ABS_OFFSET=0x00000078    result[1E]=0x11111111
. ABS_OFFSET=0x0000007C    result[1F]=0x11111111

 


BYTE 0:
    Start:         HC=0x02 ABS=0x0C
    End:         HC=0x04 ABS=0x44
    Mean:         HC=0x03 ABS=0x28
    End-0.5*tCK:     HC=0x03 ABS=0x44
    Final:         HC=0x03 ABS=0x44
BYTE 1:
    Start:         HC=0x01 ABS=0x70
    End:         HC=0x04 ABS=0x30
    Mean:         HC=0x03 ABS=0x10
    End-0.5*tCK:     HC=0x03 ABS=0x30
    Final:         HC=0x03 ABS=0x30
BYTE 2:
    Start:         HC=0x01 ABS=0x5C
    End:         HC=0x04 ABS=0x1C
    Mean:         HC=0x02 ABS=0x7B
    End-0.5*tCK:     HC=0x03 ABS=0x1C
    Final:         HC=0x03 ABS=0x1C
BYTE 3:
    Start:         HC=0x00 ABS=0x40
    End:         HC=0x04 ABS=0x28
    Mean:         HC=0x02 ABS=0x34
    End-0.5*tCK:     HC=0x03 ABS=0x28
    Final:         HC=0x03 ABS=0x28
BYTE 4:
    Start:         HC=0x00 ABS=0x1C
    End:         HC=0x04 ABS=0x38
    Mean:         HC=0x02 ABS=0x2A
    End-0.5*tCK:     HC=0x03 ABS=0x38
    Final:         HC=0x03 ABS=0x38
BYTE 5:
    Start:         HC=0x02 ABS=0x00
    End:         HC=0x04 ABS=0x28
    Mean:         HC=0x03 ABS=0x14
    End-0.5*tCK:     HC=0x03 ABS=0x28
    Final:         HC=0x03 ABS=0x28
BYTE 6:
    Start:         HC=0x01 ABS=0x30
    End:         HC=0x03 ABS=0x5C
    Mean:         HC=0x02 ABS=0x46
    End-0.5*tCK:     HC=0x02 ABS=0x5C
    Final:         HC=0x02 ABS=0x5C
BYTE 7:
    Start:         HC=0x00 ABS=0x40
    End:         HC=0x04 ABS=0x1C
    Mean:         HC=0x02 ABS=0x2E
    End-0.5*tCK:     HC=0x03 ABS=0x1C
    Final:         HC=0x03 ABS=0x1C

 

DQS calibration MMDC0 MPDGCTRL0 = 0x03300344, MPDGCTRL1 = 0x0328031C

 

DQS calibration MMDC1 MPDGCTRL0 = 0x03280338, MPDGCTRL1 = 0x031C025C

 

Note: Array result[] holds the DRAM test result of each byte.  
      0: test pass.  1: test fail  
      4 bits respresent the result of 1 byte.    
      result 00000001:byte 0 fail.
      result 00000011:byte 0, 1 fail.

 

Starting Read calibration...

 

ABS_OFFSET=0x00000000    result[00]=0x11111111
ABS_OFFSET=0x04040404    result[01]=0x11111111
ABS_OFFSET=0x08080808    result[02]=0x11111111
ABS_OFFSET=0x0C0C0C0C    result[03]=0x11111111
ABS_OFFSET=0x10101010    result[04]=0x11111111
ABS_OFFSET=0x14141414    result[05]=0x01011111
ABS_OFFSET=0x18181818    result[06]=0x00011001
ABS_OFFSET=0x1C1C1C1C    result[07]=0x00011000
ABS_OFFSET=0x20202020    result[08]=0x00010000
ABS_OFFSET=0x24242424    result[09]=0x00000000
ABS_OFFSET=0x28282828    result[0A]=0x00000000
ABS_OFFSET=0x2C2C2C2C    result[0B]=0x00000000
ABS_OFFSET=0x30303030    result[0C]=0x00000000
ABS_OFFSET=0x34343434    result[0D]=0x00000000
ABS_OFFSET=0x38383838    result[0E]=0x00000000
ABS_OFFSET=0x3C3C3C3C    result[0F]=0x00000000
ABS_OFFSET=0x40404040    result[10]=0x00000000
ABS_OFFSET=0x44444444    result[11]=0x00000000
ABS_OFFSET=0x48484848    result[12]=0x00000010
ABS_OFFSET=0x4C4C4C4C    result[13]=0x00100010
ABS_OFFSET=0x50505050    result[14]=0x00100111
ABS_OFFSET=0x54545454    result[15]=0x01100111
ABS_OFFSET=0x58585858    result[16]=0x11100111
ABS_OFFSET=0x5C5C5C5C    result[17]=0x11110111
ABS_OFFSET=0x60606060    result[18]=0x11111111
ABS_OFFSET=0x64646464    result[19]=0x11111111
ABS_OFFSET=0x68686868    result[1A]=0x11111111
ABS_OFFSET=0x6C6C6C6C    result[1B]=0x11111111
ABS_OFFSET=0x70707070    result[1C]=0x11111111
ABS_OFFSET=0x74747474    result[1D]=0x11111111
ABS_OFFSET=0x78787878    result[1E]=0x11111111
ABS_OFFSET=0x7C7C7C7C    result[1F]=0x11111111

 

Byte 0: (0x1c - 0x4c), middle value:0x34
Byte 1: (0x18 - 0x44), middle value:0x2e
Byte 2: (0x18 - 0x4c), middle value:0x32
Byte 3: (0x20 - 0x5c), middle value:0x3e
Byte 4: (0x24 - 0x58), middle value:0x3e
Byte 5: (0x14 - 0x48), middle value:0x2e
Byte 6: (0x18 - 0x50), middle value:0x34
Byte 7: (0x14 - 0x54), middle value:0x34

 

MMDC0 MPRDDLCTL = 0x3E322E34, MMDC1 MPRDDLCTL = 0x34342E3E

 

Starting Write calibration...

 

ABS_OFFSET=0x00000000    result[00]=0x11111111
ABS_OFFSET=0x04040404    result[01]=0x11111111
ABS_OFFSET=0x08080808    result[02]=0x10110111
ABS_OFFSET=0x0C0C0C0C    result[03]=0x10110110
ABS_OFFSET=0x10101010    result[04]=0x10100000
ABS_OFFSET=0x14141414    result[05]=0x10000000
ABS_OFFSET=0x18181818    result[06]=0x00000000
ABS_OFFSET=0x1C1C1C1C    result[07]=0x00000000
ABS_OFFSET=0x20202020    result[08]=0x00000000
ABS_OFFSET=0x24242424    result[09]=0x00000000
ABS_OFFSET=0x28282828    result[0A]=0x00000000
ABS_OFFSET=0x2C2C2C2C    result[0B]=0x00000000
ABS_OFFSET=0x30303030    result[0C]=0x00000000
ABS_OFFSET=0x34343434    result[0D]=0x00000000
ABS_OFFSET=0x38383838    result[0E]=0x00000000
ABS_OFFSET=0x3C3C3C3C    result[0F]=0x00000000
ABS_OFFSET=0x40404040    result[10]=0x00000000
ABS_OFFSET=0x44444444    result[11]=0x00000000
ABS_OFFSET=0x48484848    result[12]=0x00000000
ABS_OFFSET=0x4C4C4C4C    result[13]=0x00000000
ABS_OFFSET=0x50505050    result[14]=0x00000000
ABS_OFFSET=0x54545454    result[15]=0x00000000
ABS_OFFSET=0x58585858    result[16]=0x00000000
ABS_OFFSET=0x5C5C5C5C    result[17]=0x00000000
ABS_OFFSET=0x60606060    result[18]=0x01000000
ABS_OFFSET=0x64646464    result[19]=0x01000011
ABS_OFFSET=0x68686868    result[1A]=0x01111111
ABS_OFFSET=0x6C6C6C6C    result[1B]=0x01111111
ABS_OFFSET=0x70707070    result[1C]=0x11111111
ABS_OFFSET=0x74747474    result[1D]=0x11111111
ABS_OFFSET=0x78787878    result[1E]=0x11111111
ABS_OFFSET=0x7C7C7C7C    result[1F]=0x11111111

 

Byte 0: (0x0c - 0x60), middle value:0x36
Byte 1: (0x10 - 0x60), middle value:0x38
Byte 2: (0x10 - 0x64), middle value:0x3a
Byte 3: (0x08 - 0x64), middle value:0x36

 

Byte 5: (0x14 - 0x64), middle value:0x3c
Byte 6: (0x08 - 0x5c), middle value:0x32
Byte 7: (0x18 - 0x6c), middle value:0x42

 

MMDC0 MPWRDLCTL = 0x363A3836,MMDC1 MPWRDLCTL = 0x42323C3A

 


   MMDC registers updated from calibration

 

   Write leveling calibration
   MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x001F0019
   MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x001F0023
   MMDC_MPWLDECTRL0 ch1 (0x021b480c) = 0x0018001F
   MMDC_MPWLDECTRL1 ch1 (0x021b4810) = 0x0006001F

 

   Read DQS Gating calibration
   MPDGCTRL0 PHY0 (0x021b083c) = 0x03300344
   MPDGCTRL1 PHY0 (0x021b0840) = 0x0328031C
   MPDGCTRL0 PHY1 (0x021b483c) = 0x03280338
   MPDGCTRL1 PHY1 (0x021b4840) = 0x031C025C

 

   Read calibration
   MPRDDLCTL PHY0 (0x021b0848) = 0x3E322E34
   MPRDDLCTL PHY1 (0x021b4848) = 0x34342E3E

 

   Write calibration
   MPWRDLCTL PHY0 (0x021b0850) = 0x363A3836
   MPWRDLCTL PHY1 (0x021b4850) = 0x42323C3A

 


Success: DDR calibration completed!!!

 

 

 

============================================
        DDR Stress Test (2.6.0)
        Build: Aug  1 2017, 17:33:25
        NXP Semiconductors.

 

DDR Stress Test Iteration 1
Current Temperature: 53
============================================

 

DDR Freq: 135 MHz
t0.1: data is addr test
Address of failure(step2): 0x10000000
Data was: 0x00000010
But pattern  should match address
Error: failed to run stress test!!!

 


        0x0        0x4        0x8        0xC
        ----------------------------------------------------------------------------------------------------------------
0x10000000:    0x00000010    
memory read is done

Outcomes