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K64 TX FIFO Underflow EDMA SPI Slave

Question asked by Adam Kent on Dec 11, 2017
Latest reply on Feb 8, 2018 by Adam Kent

I have a K64 SPI Slave using EDMA drivers from KSDK 1.3.0. The SPI master is sending 8K blocks of data (MODE0, 16 bit words) with a 10MHz SPI clock in what appears to be 128 byte bursts. My highest priority MQX task is spinning in a while loop waiting for 8K blocks of data from the master using call to DSPI_DRV_EdmaSlaveTransferBlocking. The master waits 2 milliseconds in between transfers and I have verified that the K64 is always ready to receive before the master initiates a transfer.

 

I turned on RX FIFO Overflow and TX FIFO Underflow interrupts because I was losing SPI data between master/slave. I am occasionally getting TX FIFO Underflow interrupts to occur. I added error handling and early abort to the DSPI_DRV_EdmaSlaveTransferBlocking API function so that I can recover from this condition, but I would like to know why this interrupt is occurring so that I may attempt to fix the problem. My understanding is that the DSPI/EDMA transfers are completely hardware driven at this point.

 

The K64 is running at 120MHz with a 60MHz bus clock.  I am using DSPI channel 0 in DMA mode. I have fixed priority DMA channels 0 and 1 for RX and TX respectively. The DMA interrupts are both set to high priority. No other peripherals  (UART, I2C, etc.) are active during the SPI transfers.

 

All peripherals are configured using Processor Expert.

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