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On-Line BIST for the MPC5748G:

Question asked by Nathan Coerper on Dec 7, 2017

I have a created a program that runs only the MBIST test for the MPC5748G.

The issue is that after the system completes the MBIST and I try to read the On-Line Status and On-Line End Flag registers the system appears to reset.

I am not running any of the Off-Line BIST the BYP bit is set in the STCU2_RUN register.

I do have the debugger connected and when I look at the STUC2 Registers using the Memory Browser none of the error flags are set in the ERR_STAT register.

 

Any help or information would be helpful.

Nathan

 

Here is a code:

__attribute__ ((section(".text")))
int main(void)
{
    static volatile uint32_t Off_Line_MBIST_StatusL = 0x12345678UL;
    static volatile uint32_t Off_Line_MBIST_StatusM = 0x12345678UL;
    static volatile uint32_t Off_Line_MBIST_StatusH = 0x12345678UL;
    static volatile uint32_t Off_Line_MBIST_EndFlagL = 0x12345678UL;
    static volatile uint32_t Off_Line_MBIST_EndFlagM = 0x12345678UL;
    static volatile uint32_t Off_Line_MBIST_EndFlagH = 0x12345678UL;

 


    static volatile uint32_t On_Line_MBIST_StatusL = 0x12345678UL;
    static volatile uint32_t On_Line_MBIST_StatusM = 0x12345678UL;
    static volatile uint32_t On_Line_MBIST_StatusH = 0x12345678UL;
    static volatile uint32_t On_Line_MBIST_EndFlagL = 0x12345678UL;
    static volatile uint32_t On_Line_MBIST_EndFlagM = 0x12345678UL;
    static volatile uint32_t On_Line_MBIST_EndFlagH = 0x12345678UL;

 

    static volatile uint32_t Error_Stat = 0x12345678UL;
    static volatile uint32_t Error_FM = 0x12345678UL;
    static volatile uint32_t loop_cnt = 0UL;

 

    /* Select FXOSC as input to the PLL */
    MC_CGM.AC5_SC.B.SELCTL = 1U;

 

    PLLDIG.PLLDV.B.PREDIV = 2U; /* ------------------ CONFIGURE PLL ------------------- */
    PLLDIG.PLLDV.B.MFD = 16U; /* VCO = 40 MHz / PREDIV * (MFD + (MFN / (MFDEN + 1)))  */
    PLLDIG.PLLFD.B.MFN = 0U; /*     = 40 MHz /      2 * (16  + (  0 / (    1 + 1)))  */
    PLLDIG.PLLCAL3.B.MFDEN = 1U; /*     = 320 MHz                                        */

 

    PLLDIG.PLLDV.B.RFDPHI = 0u; /* PHI  = VC0 / 2 = 160 MHz */
    PLLDIG.PLLDV.B.RFDPHI1 = 1u; /* PHI1 = VC0 / 4 =  80 MHz */

 

    /* CONFIGURE DRUN MODE */
    MC_ME.DRUN_MC.B.PLLON = 1u; /* Enable the PLL */
    MC_ME.DRUN_MC.B.FXOSCON = 1u; /* Enable the OSC */
    MC_ME.DRUN_MC.B.SYSCLK = 2u; /* Use FMPLL PHI_0 for the system clock */

 

    /* TRANSITION TO DRUN MODE */
    MC_ME.MCTL.R = SYS_MCTL_DRUN | SYS_MCTL_KEY;
    MC_ME.MCTL.R = SYS_MCTL_DRUN | SYS_MCTL_INV_KEY;

 

    /* Activate peripheral clock under modes of SAFE, DRUN, RUN0, RUN1, RUN2, RUN3 */
    MC_ME.RUN_PC[0].R = 0x000000fcUL;

 

    /* Apply the new configuration */
    while (MC_ME.GS.B.S_MTRANS == 1u)
    {

 

    }

 

    /* Do not step through or halt the sequence from this point!! The STCU keys will time out if this happens*/
    /* Write on-line unlock keys to the STCU */
    STCU2.SKC.R = 0x753F924EUL;
    STCU2.SKC.R = 0x8AC06DB1UL;

 

    if(STCU2.CFG.B.WRP != 0x00u)        // Is the Write Protection Bit set?
    {
        STCU2.CFG.B.WRP = 0x00;         // Clear the Write Protection Bit.
    }

 

    /* Configure MBIST Control registers */
    STCU2.MB_CTRL[0].R = 0x91000000;        /* MBIST CTRL00 Run concurrently, next in sequence is MBIST 1 */
    STCU2.MB_CTRL[1].R = 0x92000000;        /* MBIST CTRL01 Run concurrently, next in sequence is MBIST 2 */
    STCU2.MB_CTRL[2].R = 0x93000000;        /* MBIST CTRL02 Run concurrently, next in sequence is MBIST 3 */
    STCU2.MB_CTRL[3].R = 0x94000000;        /* MBIST CTRL03 Run concurrently, next in sequence is MBIST 4 */
    STCU2.MB_CTRL[4].R = 0x95000000;        /* MBIST CTRL04 Run concurrently, next in sequence is MBIST 5 */
    STCU2.MB_CTRL[5].R = 0x96000000;        /* MBIST CTRL05 Run concurrently, next in sequence is MBIST 6 */
    STCU2.MB_CTRL[6].R = 0x97000000;        /* MBIST CTRL06 Run concurrently, next in sequence is MBIST 7 */
    STCU2.MB_CTRL[7].R = 0x98000000;        /* MBIST CTRL07 Run concurrently, next in sequence is MBIST 8 */
    STCU2.MB_CTRL[8].R = 0x99000000;        /* MBIST CTRL08 Run concurrently, next in sequence is MBIST 9 */
    STCU2.MB_CTRL[9].R = 0x9A000000;        /* MBIST CTRL09 Run concurrently, next in sequence is MBIST 10 */
    STCU2.MB_CTRL[10].R = 0x9B000000;       /* MBIST CTRL10 Run concurrently, next in sequence is MBIST 11 */

 

    /* Write key 2 to service the watchdog */
    STCU2.SKC.R = 0x8AC06DB1;

 

    STCU2.MB_CTRL[11].R = 0x9C000000;       /* MBIST CTRL11 Run concurrently, next in sequence is MBIST 12 */
    STCU2.MB_CTRL[12].R = 0x9D000000;       /* MBIST CTRL12 Run concurrently, next in sequence is MBIST 13 */
    STCU2.MB_CTRL[13].R = 0x9E000000;       /* MBIST CTRL13 Run concurrently, next in sequence is MBIST 14 */
    STCU2.MB_CTRL[14].R = 0x9F000000;       /* MBIST CTRL14 Run concurrently, next in sequence is MBIST 15 */
    STCU2.MB_CTRL[15].R = 0xA0000000;       /* MBIST CTRL15 Run concurrently, next in sequence is MBIST 16 */
    STCU2.MB_CTRL[16].R = 0xA1000000;       /* MBIST CTRL16 Run concurrently, next in sequence is MBIST 17 */
    STCU2.MB_CTRL[17].R = 0xA2000000;       /* MBIST CTRL17 Run concurrently, next in sequence is MBIST 18 */
    STCU2.MB_CTRL[18].R = 0xA3000000;       /* MBIST CTRL18 Run concurrently, next in sequence is MBIST 19 */
    STCU2.MB_CTRL[19].R = 0xA4000000;       /* MBIST CTRL19 Run concurrently, next in sequence is MBIST 20 */
    STCU2.MB_CTRL[20].R = 0xA5000000;       /* MBIST CTRL20 Run concurrently, next in sequence is MBIST 21 */

 

    /* Write key 2 to service the watchdog */
    STCU2.SKC.R = 0x8AC06DB1;

 

    STCU2.MB_CTRL[21].R = 0xA6000000;       /* MBIST CTRL21 Run concurrently, next in sequence is MBIST 22 */
    STCU2.MB_CTRL[22].R = 0xA7000000;       /* MBIST CTRL22 Run concurrently, next in sequence is MBIST 23 */
    STCU2.MB_CTRL[23].R = 0xA8000000;       /* MBIST CTRL23 Run concurrently, next in sequence is MBIST 24 */
    STCU2.MB_CTRL[24].R = 0xA9000000;       /* MBIST CTRL24 Run concurrently, next in sequence is MBIST 25 */
    STCU2.MB_CTRL[25].R = 0xAA000000;       /* MBIST CTRL25 Run concurrently, next in sequence is MBIST 26 */
    STCU2.MB_CTRL[26].R = 0xAB000000;       /* MBIST CTRL26 Run concurrently, next in sequence is MBIST 27 */
    STCU2.MB_CTRL[27].R = 0xAC000000;       /* MBIST CTRL27 Run concurrently, next in sequence is MBIST 28 */
    STCU2.MB_CTRL[28].R = 0xAD000000;       /* MBIST CTRL28 Run concurrently, next in sequence is MBIST 29 */
    STCU2.MB_CTRL[29].R = 0xAE000000;       /* MBIST CTRL29 Run concurrently, next in sequence is MBIST 30 */
    STCU2.MB_CTRL[30].R = 0xAF000000;       /* MBIST CTRL30 Run concurrently, next in sequence is MBIST 31 */
    STCU2.MB_CTRL[31].R = 0xB0000000;       /* MBIST CTRL31 Run concurrently, next in sequence is MBIST 32 */
    STCU2.MB_CTRL[32].R = 0xB1000000;       /* MBIST CTRL32 Run concurrently, next in sequence is MBIST 33 */
    STCU2.MB_CTRL[33].R = 0xB2000000;       /* MBIST CTRL33 Run concurrently, next in sequence is MBIST 34 */
    STCU2.MB_CTRL[34].R = 0xB3000000;       /* MBIST CTRL34 Run concurrently, next in sequence is MBIST 35 */
    STCU2.MB_CTRL[35].R = 0xB4000000;       /* MBIST CTRL35 Run concurrently, next in sequence is MBIST 36 */
    STCU2.MB_CTRL[36].R = 0xB5000000;       /* MBIST CTRL36 Run concurrently, next in sequence is MBIST 37 */
    STCU2.MB_CTRL[37].R = 0xB6000000;       /* MBIST CTRL37 Run concurrently, next in sequence is MBIST 38 */
    STCU2.MB_CTRL[38].R = 0x37000000;       /* MBIST CTRL38 Run concurrently, next in sequence is MBIST 39 -
                                            This is set to sequential so that the next group runs sequentially
                                            to this group */

 

    /* Write key 2 to service the watchdog */
    STCU2.SKC.R = 0x8AC06DB1;

 

    /*Group 2- Partitions 39 to 75. Overlay RAM, IOP RAM, HSM RAM and DMA RAM*/

 

    STCU2.MB_CTRL[39].R = 0xB8000000;       /* MBIST CTRL39 Run concurrently, next in sequence is MBIST 40 */
    STCU2.MB_CTRL[40].R = 0xB9000000;       /* MBIST CTRL40 Run concurrently, next in sequence is MBIST 41 */
    STCU2.MB_CTRL[41].R = 0xBA000000;       /* MBIST CTRL41 Run concurrently, next in sequence is MBIST 42 */
    STCU2.MB_CTRL[42].R = 0xBB000000;       /* MBIST CTRL42 Run concurrently, next in sequence is MBIST 43 */
    STCU2.MB_CTRL[43].R = 0xBC000000;       /* MBIST CTRL43 Run concurrently, next in sequence is MBIST 44 */
    STCU2.MB_CTRL[44].R = 0xBD000000;       /* MBIST CTRL44 Run concurrently, next in sequence is MBIST 45 */
    STCU2.MB_CTRL[45].R = 0xBE000000;       /* MBIST CTRL45 Run concurrently, next in sequence is MBIST 46 */
    STCU2.MB_CTRL[46].R = 0xBF000000;       /* MBIST CTRL46 Run concurrently, next in sequence is MBIST 47 */
    STCU2.MB_CTRL[47].R = 0xC0000000;       /* MBIST CTRL47 Run concurrently, next in sequence is MBIST 48 */
    STCU2.MB_CTRL[48].R = 0xC1000000;       /* MBIST CTRL48 Run concurrently, next in sequence is MBIST 49 */
    STCU2.MB_CTRL[49].R = 0xC2000000;       /* MBIST CTRL49 Run concurrently, next in sequence is MBIST 50 */
    STCU2.MB_CTRL[50].R = 0xC3000000;       /* MBIST CTRL50 Run concurrently, next in sequence is MBIST 51 */
    STCU2.MB_CTRL[51].R = 0xC4000000;       /* MBIST CTRL51 Run concurrently, next in sequence is MBIST 52 */
    STCU2.MB_CTRL[52].R = 0xC5000000;       /* MBIST CTRL52 Run concurrently, next in sequence is MBIST 53 */
    STCU2.MB_CTRL[53].R = 0xC6000000;       /* MBIST CTRL53 Run concurrently, next in sequence is MBIST 54 */
    STCU2.MB_CTRL[54].R = 0xC7000000;       /* MBIST CTRL54 Run concurrently, next in sequence is MBIST 55 */
    STCU2.MB_CTRL[55].R = 0xC8000000;       /* MBIST CTRL55 Run concurrently, next in sequence is MBIST 56 */
    STCU2.MB_CTRL[56].R = 0xC9000000;       /* MBIST CTRL56 Run concurrently, next in sequence is MBIST 57 */
    STCU2.MB_CTRL[57].R = 0xCA000000;       /* MBIST CTRL57 Run concurrently, next in sequence is MBIST 58 */

 

    /* Write key 2 to service the watchdog */
    STCU2.SKC.R = 0x8AC06DB1;

 

    STCU2.MB_CTRL[58].R = 0xCB000000;       /* MBIST CTRL58 Run concurrently, next in sequence is MBIST 59 */
    STCU2.MB_CTRL[59].R = 0xCC000000;       /* MBIST CTRL59 Run concurrently, next in sequence is MBIST 60 */
    STCU2.MB_CTRL[60].R = 0xCD000000;       /* MBIST CTRL60 Run concurrently, next in sequence is MBIST 61 */
    STCU2.MB_CTRL[61].R = 0xCE000000;       /* MBIST CTRL61 Run concurrently, next in sequence is MBIST 62 */
    STCU2.MB_CTRL[62].R = 0xCF000000;       /* MBIST CTRL62 Run concurrently, next in sequence is MBIST 63 */
    STCU2.MB_CTRL[63].R = 0xD0000000;       /* MBIST CTRL63 Run concurrently, next in sequence is MBIST 64 */
    STCU2.MB_CTRL[64].R = 0xD1000000;       /* MBIST CTRL64 Run concurrently, next in sequence is MBIST 65 */
    STCU2.MB_CTRL[65].R = 0xD2000000;       /* MBIST CTRL65 Run concurrently, next in sequence is MBIST 66 */
    STCU2.MB_CTRL[66].R = 0xD3000000;       /* MBIST CTRL66 Run concurrently, next in sequence is MBIST 67 */
    STCU2.MB_CTRL[67].R = 0xD4000000;       /* MBIST CTRL67 Run concurrently, next in sequence is MBIST 68 */
    STCU2.MB_CTRL[68].R = 0xD5000000;       /* MBIST CTRL68 Run concurrently, next in sequence is MBIST 69 */
    STCU2.MB_CTRL[69].R = 0xD6000000;       /* MBIST CTRL69 Run concurrently, next in sequence is MBIST 70 */
    STCU2.MB_CTRL[70].R = 0xD7000000;       /* MBIST CTRL70 Run concurrently, next in sequence is MBIST 71 */
    STCU2.MB_CTRL[71].R = 0xD8000000;       /* MBIST CTRL71 Run concurrently, next in sequence is MBIST 72 */
    STCU2.MB_CTRL[72].R = 0xD9000000;       /* MBIST CTRL72 Run concurrently, next in sequence is MBIST 73 */
    STCU2.MB_CTRL[73].R = 0xDA000000;       /* MBIST CTRL73 Run concurrently, next in sequence is MBIST 74 */
    STCU2.MB_CTRL[74].R = 0xDB000000;       /* MBIST CTRL74 Run concurrently, next in sequence is MBIST 75 */
    STCU2.MB_CTRL[75].R = 0x7F000000;       /* MBIST CTRL75 Run concurrently */

 

    /* Write key 2 to service the watchdog */
    STCU2.SKC.R = 0x8AC06DB1;

 

    STCU2.MBUFML.R = 0x0;           /* Configure all faults as recoverable in this example */
    STCU2.MBUFMM.R = 0x0;           /* Configure all faults as recoverable in this example */
    STCU2.MBUFMH.R = 0x0;           /* Configure all faults as recoverable in this example */

 

    /* Set Watchdog timeout Config */
    STCU2.WDG.R = 0xFFFFFFFF;                   /* Watchdog time out to Max value */

 

    STCU2.CFG.R = 0x10000003;                   /* MBIST PMOS TEST is disabled for The Full online test sequence */
                                                /* PLL = 160 MHz / 4 = 40MHz */

 

    STCU2.RUNSW.R = 0x00000201;    // Run MBIST Only with PLL Enabled.

 

    while (STCU2.RUNSW.B.RUNSW == 1)
    {
        loop_cnt++;
    }

 

    /* Read MBIST On-Line Statue Registers */
    On_Line_MBIST_StatusL = STCU2.MBSLSW.R;        // <<<< Break Point Set Here
    On_Line_MBIST_StatusM = STCU2.MBSMSW.R;
    On_Line_MBIST_StatusH = STCU2.MBSHSW.R;
    On_Line_MBIST_EndFlagL = STCU2.MBELSW.R;        // <<<< Reset Occurs Here
    On_Line_MBIST_EndFlagM = STCU2.MBEMSW.R;
    On_Line_MBIST_EndFlagH = STCU2.MBEHSW.R;

 

    /* Read STCU2 Error Registers */
    Error_Stat = STCU2.ERR_STAT.R;
    Error_FM = STCU2.ERR_FM.R;

 

    /* Read MBIST Off-Line Status Registers */
    Off_Line_MBIST_StatusL = STCU2.MBSL.R;
    Off_Line_MBIST_StatusM = STCU2.MBSM.R;
    Off_Line_MBIST_StatusH = STCU2.MBSH.R;
    Off_Line_MBIST_EndFlagL = STCU2.MBEL.R;
    Off_Line_MBIST_EndFlagM = STCU2.MBEM.R;
    Off_Line_MBIST_EndFlagH = STCU2.MBEH.R;
}

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