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eSPI status bits in SPIE do not keep up with FIFO state

Question asked by Don Heyse on Dec 7, 2017
Latest reply on Dec 8, 2017 by Don Heyse

I'm trying to use the eSPI in polling mode to access a device connected to SPI CS1 on a T1042 RDB devkit and I'm having issues monitoring the TX FIFO status bits in the SPIE register.  In particular, I've noticed that bytes added to the FIFO do not show up right away in the SPIE TXCNT and TNF status fields.  For example, if I fill the FIFO with 32 bytes in preparation for starting a transmit frame and then read the SPIE, I see TNF is still set and TXCNT is 6 or 7 instead of 0.  Eventually a subsequent SPIE read will show the correct values.  Is there any information on how long I should wait after writing to the FIFO before the status in the SPIE is up to date?


This becomes more of an issue once the frame starts transmitting and I have to keep the FIFO fed, because I don't want to overfill the FIFO (and lose data) by reading SPIE too quickly and having it say there's still space in the FIFO when it its actually full.