AnsweredAssumed Answered

T1024 DDR ECC SBEC interrupt

Question asked by Eduard Kromskoy on Dec 6, 2017
Latest reply on Dec 6, 2017 by ufedor

I am looking for clarification on some phrase in T1024 data sheet. Paragraph 14.4.77 Single-Bit ECC memory error management (DDR_ERR_SBE) has table that states for SBEC following description:

"Single-bit error counter. Indicates the number of single-bit errors detected and corrected since the last
error report. If single-bit error reporting is enabled, an error is reported and an interrupt is generated when
this value equals SBET. SBEC is automatically cleared when the threshold value is reached. This counter
is only incremented when single-bit errors which are not automatically fixed by the controller are detected."


The very last sentence contradicts to what was said before. So, is this counter incremented when SBE detected and corrected? Or should I somehow disable automatically fixing in order for this counter to be incremented? Then what is suggested algorithm to correct this SBE to proceed forward till threshold value is reached? 


We planned to use SBET/SBEC and interrupts in hope that SBE would be detected, corrected and SBEC incremented. We need this for device stress tests in chamber where SBE and MBE are likely to happen and need some measurements. 


Thank you,