My follow code:
1. Refresh counter
2. Stop SWT immediately (disable)
3. Read counter
But sometimes the counter value reaches to timeout value, sometimes it not.
- In RM:
"When the watchdog is disabled (SWT_CR[WEN] is 0), this field shows the value of the internal down counter. When the watchdog is enabled (SWT_CR[WEN] is 1), this field is cleared (the value is 0x0000_0000). Values in this field can lag behind the internal counter value for up to 6 system clock cycles plus 8 counter clock cycles. Therefore, the value read from this field immediately after disabling the watchdog may be higher than the actual value of the internal counter."
-> "Higher" is CO = 1000 -> so actual value = 1008? or 992?
-> And whether or not SWT need a bit time to reload operation? So if stop instantly, the reload operation is ignored?
The answer is SWT design limitation?
Accesses to SWT registers occur with no peripheral bus wait states. (The peripheral bus
bridge may add one or more system wait states.) However, due to synchronization logic
in the SWT design, recognition of the "service sequence" or "configuration changes" may
require up to three system plus seven counter clock cycles.