HCS08 reset pin goes to VDD/2 for no apparent reason ??

[Diode]

Hello,

I am quite puzzled here. I hope someone can help.

Ok, first my environment:

- We are using the MC9S08GT32CFB mask 3L31R. It is powered at VDD=3.0 volts by a buck regulator which gets its power from 3XAA batteries.

- All errata (when applicable) for this IC have been applied, especially the one related to the reset pin which asks for an external 4.7K to 10K to VDD + 0,1uF cap. I have a 10K + 0.1uF cap.

- The GT32 uses stop mode 3 with internal ICG with KBI and IRQ as inputs pins and enabled for waking up on interrupts. BKGD and LVD functions are disabled.

- All unused pins are set as outputs (including the ones from the GT60 die not bounded to the GT32 package)

The problem:

During normal operation, one out of every 10 ICs goes dead or hangs for no reason. When the IC dies, the reset pin voltage reads approx 1.6 volts (not 3V as it should) and power consumption increases. When this happens, I shut down all power to the board and re-apply it. After multiple attempts of cycling the power on and off, the IC finally reboots BUT the same problem remains, that is, the reset pin stays around 1.6 volts and system power consumption may go from 200uA to 3 mA (normal system consumption in stop 3 mode is 15uA). So obviously here, the board is very unstable as its reset pin seems floating. But even in this state, firmware may still be running fine. So far, the only way to fix this is to replace the IC completely.

It would seem the Reset input is in latch-up or is sinking my 10K pull-up ??!!

The board may run for several months before this behavior starts to show up. Operating temperature has no effect and the board which only runs at 4Mhz internally with no othe external buses or high speed lines is enclosed in a metallic cage so I doubt ESD or EMC interference could have an effect.

Any ideas ? 

[bigmac]

Hello, and welcome to the forum.

Firstly, I see that you have disabled the LVD reset operation?  The operation of the LVD would seem essential for your application, particularly with battery operation.

I note that the reset pin for the device you are using is bi-directional.  This means that the pin may be driven low by internal conditions that result in a reset.  Could there be any possibility that the external pullup resistor value on the reset pin is erroneously much lower than you have assumed?  This might prevent the pin from being pulled to the required logic low level.  I can't seem to find the sink current capability for the reset pin within the datasheet.

What type of AA cells are you using - standard alkaline type?  Typically, these might be considered exhausted for a cell voltage of 1.0, assuming the loading is light.  However, you will likely need to consider replacement at a somewhat higher voltage, and this will depend on the drop-out voltage of the regulator you are using.  It will need to have very low dropout voltage.  The situation would be exacerbated if you have short term heavy loading.

Have you measured the output voltage of the regulator during the fault condition?

Regards,

Mac

[Diode]

Hello bigmac,

Thanks for the greetings and super fast response !

The LVD was disabled since the buck regulator keeps VDD at 3 volts even though the batteries drop from 4.5 volts (3AA @ 1.5V) to 3.3 volts 1.1-1.2V (where I do consider them dead). So, the LVD with its trip voltage at 2.1/2.2 volts is no use to me. Low bat detection is performed by another circuit.

Batterries are AA type, either alkaline or lithium. The buck/switching regulator I am using will "follow" the input voltage even when the voltage drops below its setpoint value (acts as a pass-thru once input is below setpoint)

As for the problem I am having...

Good point but the IC voltage (VDD) is the first thing I looked at. Everything is fine. A clean and stable voltage. As for the pull-up, this is also something I have checked. And yes, you are right, the reset pin is bi-dir but I don't see why it would all of a sudden revert to an output during normal operation. And if it did, I would assume it'd be able to sink my 10K pull-up to ground, not to 1.6/1.7 or even 1.8 volts.

There is nothing else connected to the Reset line, just a switch, a 10K pull-up and a 0.1uF cap. We've had boards that were out in the field for almost a year before they came back with this problem.

Power consumption is also checked in production before it is shipped out. However, we have never checked what the Reset pin voltage looked like on those faulty ICs when they were released. So perhaps this problem was there all along and we were just lucky that the Reset voltage was just high enough to be considered high by the IC.

This is becoming a huge issue here. Of course we're going to use a newer chip rev, but for all those assembled boards (and those already shipped) this is not a good news. Hopefully at least I can understand what is going on.

The only thing I can think of is that those ICs were either damaged by ESD in production/handling or at our subcontractor (for conformal coating).

Thanks again for all precious inputs...

[BasePointer]

Hi,

We used 10K and 100nF RC on RESET pin such as suggested by the datasheet and lived some startup problems. I think the datasheets are wrong. Try 1K and 1nF combination as RC filer on the reset pin. We didn't live such as problem after this.

I hope this helps.

Good luck,

BP.

[Diode]

---

BasePointer wrote:

Hi,

We used 10K and 100nF RC on RESET pin such as suggested by the datasheet and lived some startup problems. I think the datasheets are wrong. Try 1K and 1nF combination as RC filer on the reset pin. We didn't live such as problem after this.

I hope this helps.

Good luck,

BP.

---

Hello BP,

When you say, we didn't live such as problem after this" , are you saying that you actually faced the same behavior/issue I'm having, such as the IC working for sometime and then going suddenly dead with reset pin stuck around VDD/2 volts ?

If I remember correctly, if the errata is not applied the IC might no be able to detect the cause of reset (reset switch, watchdog etc..) which is not a good thing for me as I do need to know if the user pushes the reset pin.

But if you confirm you had a very similar behavior, we'll do what needs to be done. I just can't beleive though that the errata is wrong otherwise I'm assuming hundreds of people would have seen this issue ??

Thanks for your help.

Diode

[Lundin]

I don't believe the data sheets are wrong, I was having problems when I -didn't- have a 100nF cap on the reset line, I just had a small one for EMI reasons, which the mcu didn't approve of. When I swapped to 100nF, everything works fine.

Now I'm using 100nF and 10k pull-up and it works fine... though I'll admit I haven't checked the erratas in detail.

Can you determine whether the reset cause comes from the mcu itself of an external source? Ie do you have these problems still if you cut the reset line from your board and only keep the pull-up?

[Diode]

Mmmm, it seems I am dealing with an intermittent problem. After un-soldering the 0.1uF cap and re-soldering it, I am able to solve my problem about 50% of the time. and Lundin, to answer your question, the reset line is connected to a header (nothing connected to it), a switch, a 0.1uF cap and a 10K pull-up, that's all.

So far, having a 100nF + 10K pull-up does the job fine 100% of the time. I am still puzzled though about this DC voltage drop across the 10K with the 0.1uF. At one point I thought the cap (a 0603 package) could have been in fact a resistor or something, but no.

So for now, the problem seems to go away with this new mod (100nF+10K) but for how long ?

Thanks all for your help. And if you know any good ghost buster, let me know I might need one soon

Regards.

diode

[bigmac]

Hello Diode,

I would tend to disagree when you say that enabling the LVD module is "of no use" to you.  The only time it should need to be disabled is if you are using an external low voltage detect device that also provides reset of the MCU.  Otherwise, it should be used to ensure correct start-up of the MCU, particularly for cases where Vdd may ramp up very slowly.  It will hold a reset condition until Vdd is sufficiently high for correct operation at the required bus frequency.  I would expect that the capacitor value at the reset pin, whether 10n or 100n, should be non-critical.

If you are still experiencing the voltage drop at the reset pin, I might suggest that this is an abnormal condition, and might possibly indicate a faulty device whether or not operation appears to be normal.

Even though the board might be within a shielded enclosure, this may not prevent ESD and other over-voltage impulses from reaching MCU pins that are (indirectly) exposed to the "outside world".  Make sure that protection measures are adequate.  Keep in mind that, for many HCS08 devices, the maximum allowable injection current to a single pin may be as little as 0.5mA, to prevent risk of latchup and possible permanent damage.

Regards,

Mac

[Diode]

Hello bigmac,

Your point about the LVD is interesting. As stated in my other posts, I have nothing else connected to my reset line other than my 10K+cap, so no "power good" signal. However, I was under the impression that the POR was not disabled with the LVD disabled ? For instance, I do use the POR status bit in the SRS register which sets it high whenever the last reset is caused by a POR, although the LVD is off.

Are you 100% sure that the POR is completely inactive when the LVD is off ?  I simply don't see why they would let the possibility to disable the POR circuit, such an essential circuit (even if you have other means to keep reset low until power is valid) ?

As for ESD, the only path to the IC is through a keypad (silicone membrane + metallic keys), which protrudes through a metallic enclosure. We did zap the keys and the discharge seems to always flow through the enclosure, its nearest path to ground. Nevertheless, and although I have series resistor on my KB lines to limit current, ESD issues are always a possibility.

As for the problem I am having, this is still a mystery. Now all boards I have that were experiencing this issue are all working fine after unsoldering/resoldering the SAME cap (go figure) . I will have to wait for this behavior to come back in order to investigate the problem further.

Thanks for your feedbacks.

Diode

[peg]

Hi diode,

The POR still functions with LVD disabled but the fact is that the POR circuit requires the assistance of the LVD circuit to properly handle "out of spec" power conditions such as those presented during the power up/down cycle. Search this forum, you should find a few useful discussions on this. Hint: The LVD has a few different acronyms.

[wgreenwald]

Hello Diode

I know this is a long past issue, but in light of a number of your facts, flags go up for me, consideringm a problem we are having with the GT16 we are using. 

1.The RESET pin sitting at near VCC/2

2. your comment about thinking that your .1uF cap was actualy a resistor

3. removing the cap fixes the problem

4. problem doesn't show up for a number of months

A couple of questions first;

Did you use no-clean or flux core solder?

Do you conformally coat you product?

Here are my thoughts;

Even though there is an errata on a RESET problem for this family of CPU, the VCC/2 level on the RESET pin may be the key.    The residues left by flux and the soldering process, if not cleaned off completely can, over time, and when combined with moisture, cause electromigration; dendrites will grow from one terminal of a biased component (especially caps) to the other, effectively putting a "resistor" in parallel with or even shorting the cap. This proplem can take many months to show up.  Since your board is SMD, it is often easy to leave this residue under the component, even after cleaning.  This would answer items 1 & 2 above.

If the board is conformally coated, moisture takes more time to accumulate due to the conformal coating and its porosity.  The residue consists of weak organic acids which when mixed with water become ions.  The process of electromigration requires the ions to grow dendrites.  This answers item 4 above.  The acids are nomally eliminated by heat, 150 C, which make the resude inert, no dendrite growth possible.

Removing the cap and then putting it or another back would eliminate the dendrite. That would answer item 3 above.

Do a web search for the company Foresight, inc. at  www.Residues.com for more information of "dirty" boards.  It is fancinating stuff which we are currently dealing with.

Drop me an email at wgreenwald@sloanvalve.com to talk more.

Bill

[Diode]

oops, obviously here I meant a 10nF with a 10K pull-up... (which seems to work for me as 100nF / 0.1uF gives strange results.)

So long..