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lpc54618:- Target marked as not debuggable

Question asked by Subodh Mankar on Dec 5, 2017
Latest reply on Dec 11, 2017 by Kerry Zhou

Hi,

I have attached 25MHz external clock to custom board.

When I tried to give clock to pll, fro and main using external clock, board doesn't work anymore for me.

I have attached image to this post which is snapshot from Mcuxpresso IDE while I try to debug.

Following is the code generated by MCUxpresso config tool software

 

/*******************************************************************************

********************** Configuration BOARD_BootClockRUN ***********************

******************************************************************************/

/* clang-format off */

/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************

!!Configuration

name: BOARD_BootClockRUN

called_from_default_init: true

outputs:

- {id: CLKOUT_clock.outFreq, value: 25 MHz}

- {id: FRO12M_clock.outFreq, value: 12 MHz}

- {id: FROHF_clock.outFreq, value: 48 MHz}

- {id: FXCOM0_clock.outFreq, value: 12 MHz}

- {id: FXCOM1_clock.outFreq, value: 12 MHz}

- {id: FXCOM2_clock.outFreq, value: 12 MHz}

- {id: FXCOM3_clock.outFreq, value: 12 MHz}

- {id: FXCOM4_clock.outFreq, value: 12 MHz}

- {id: FXCOM5_clock.outFreq, value: 12 MHz}

- {id: FXCOM6_clock.outFreq, value: 12 MHz}

- {id: FXCOMs_CLK32K_clock.outFreq, value: 32.768 kHz}

- {id: MAIN_clock.outFreq, value: 12 MHz}

- {id: SCT_clock.outFreq, value: 12 MHz}

- {id: SPIFI_clock.outFreq, value: 12 MHz}

- {id: SYSPLL_clock.outFreq, value: 25 MHz}

- {id: System_clock.outFreq, value: 12 MHz, locked: true, accuracy: '0.001'}

settings:

- {id: SYSCON.AUDPLLCLKSEL.sel, value: SYSCON._clk_in}

- {id: SYSCON.CLKOUTSELA.sel, value: SYSCON._clk_in}

- {id: SYSCON.FXCLKSEL0.sel, value: SYSCON.fro_12m}

- {id: SYSCON.FXCLKSEL1.sel, value: SYSCON.fro_12m}

- {id: SYSCON.FXCLKSEL2.sel, value: SYSCON.fro_12m}

- {id: SYSCON.FXCLKSEL3.sel, value: SYSCON.fro_12m}

- {id: SYSCON.FXCLKSEL4.sel, value: SYSCON.fro_12m}

- {id: SYSCON.FXCLKSEL5.sel, value: SYSCON.fro_12m}

- {id: SYSCON.FXCLKSEL6.sel, value: SYSCON.fro_12m}

- {id: SYSCON.M_MULT.scale, value: '16'}

- {id: SYSCON.N_DIV.scale, value: '1'}

- {id: SYSCON.PDEC.scale, value: '16', locked: true}

- {id: SYSCON.SCTCLKSEL.sel, value: SYSCON.MAINCLKSELB}

- {id: SYSCON.SPIFICLKSEL.sel, value: SYSCON.MAINCLKSELB}

- {id: SYSCON.SYSPLLCLKSEL.sel, value: SYSCON._clk_in}

- {id: SYSCON_PDRUNCFG0_PDEN_SYS_PLL_CFG, value: Power_up}

- {id: SYSCON_PDRUNCFG0_PDEN_WDT_OSC_CFG, value: Power_up}

- {id: SYSOSCCTRL_FREQRANGE, value: High}

sources:

- {id: RTC.rtc_32k_osc.outFreq, value: 32.768 kHz, enabled: true}

- {id: SYSCON.WDT_FREQ.outFreq, value: 1 MHz}

- {id: SYSCON._clk_in.outFreq, value: 25 MHz, enabled: true}

* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/

/* clang-format on */

 

/*******************************************************************************

* Variables for BOARD_BootClockRUN configuration

******************************************************************************/

/*******************************************************************************

* Code for BOARD_BootClockRUN configuration

******************************************************************************/

void BOARD_BootClockRUN(void)

{

/*!< Set up the clock sources */

/*!< Set up FRO */

POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */

CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally

being below the voltage for current speed */

POWER_DisablePD(kPDRUNCFG_PD_SYS_OSC); /*!< Enable System Oscillator Power */

SYSCON->SYSOSCCTRL = ((SYSCON->SYSOSCCTRL & ~SYSCON_SYSOSCCTRL_FREQRANGE_MASK) | SYSCON_SYSOSCCTRL_FREQRANGE(1U)); /*!< Set system oscillator range */

POWER_SetVoltageForFreq(25000000U); /*!< Set voltage for the one of the fastest clock outputs: CLKOUT clock output */

CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */

 

/*!< Set up RTC OSC */

CLOCK_EnableClock(kCLOCK_Rtc); /*!< Enable the RTC peripheral clock */

RTC->CTRL &= ~RTC_CTRL_SWRESET_MASK; /*!< Make sure the reset bit is cleared */

RTC->CTRL &= ~RTC_CTRL_RTC_OSC_PD_MASK; /*!< Setup RTC oscillator */

SYSCON->RTCOSCCTRL = SYSCON_RTCOSCCTRL_EN_MASK; /*!< Setup RTC oscillator clock source availability to other modules */

 

/*!< Set up WDT OSC */

POWER_EnablePD(kPDRUNCFG_PD_WDT_OSC); /*!< Ensure WDT OSC is off for setup changes */

SYSCON->WDTOSCCTRL = (SYSCON_WDTOSCCTRL_DIVSEL(0) | SYSCON_WDTOSCCTRL_FREQSEL(5)); /*!< Setup WDT oscillator */

POWER_DisablePD(kPDRUNCFG_PD_WDT_OSC); /*!< Ensure WDT OSC is on */

 

/*!< Set up SYS PLL */

const pll_setup_t pllSetup = {

.pllctrl = SYSCON_SYSPLLCTRL_SELI(20U) | SYSCON_SYSPLLCTRL_SELP(9U) | SYSCON_SYSPLLCTRL_SELR(0U),

.pllmdec = (SYSCON_SYSPLLMDEC_MDEC(63U)),

.pllndec = (SYSCON_SYSPLLNDEC_NDEC(770U)),

.pllpdec = (SYSCON_SYSPLLPDEC_PDEC(11U)),

.pllRate = 25000000U,

.flags = PLL_SETUPFLAG_WAITLOCK | PLL_SETUPFLAG_POWERUP

};

CLOCK_AttachClk(kEXT_CLK_to_SYS_PLL); /*!< Set sys pll clock source*/

CLOCK_SetPLLFreq(&pllSetup); /*!< Configure PLL to the desired value */

 

/*!< Set up dividers */

CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */

CLOCK_SetClkDiv(kCLOCK_DivClkOut, 0U, true); /*!< Reset CLKOUTDIV divider counter and halt it */

CLOCK_SetClkDiv(kCLOCK_DivClkOut, 1U, false); /*!< Set CLKOUTDIV divider to value 1 */

CLOCK_SetClkDiv(kCLOCK_DivSctClk, 0U, true); /*!< Reset SCTCLKDIV divider counter and halt it */

CLOCK_SetClkDiv(kCLOCK_DivSctClk, 1U, false); /*!< Set SCTCLKDIV divider to value 1 */

 

/*!< Set up clock selectors - Attach clocks to the peripheries */

CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */

CLOCK_AttachClk(kFRO12M_to_FLEXCOMM0); /*!< Switch FLEXCOMM0 to FRO12M */

CLOCK_AttachClk(kFRO12M_to_FLEXCOMM1); /*!< Switch FLEXCOMM1 to FRO12M */

CLOCK_AttachClk(kFRO12M_to_FLEXCOMM2); /*!< Switch FLEXCOMM2 to FRO12M */

CLOCK_AttachClk(kFRO12M_to_FLEXCOMM3); /*!< Switch FLEXCOMM3 to FRO12M */

CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4); /*!< Switch FLEXCOMM4 to FRO12M */

CLOCK_AttachClk(kFRO12M_to_FLEXCOMM5); /*!< Switch FLEXCOMM5 to FRO12M */

CLOCK_AttachClk(kFRO12M_to_FLEXCOMM6); /*!< Switch FLEXCOMM6 to FRO12M */

CLOCK_AttachClk(kMCLK_to_SCT_CLK); /*!< Switch SCT_CLK to MAIN_CLK */

CLOCK_AttachClk(kMAIN_CLK_to_SPIFI_CLK); /*!< Switch SPIFI_CLK to MAIN_CLK */

CLOCK_AttachClk(kEXT_CLK_to_CLKOUT); /*!< Switch CLKOUT to EXT_CLK */

/* Set SystemCoreClock variable. */

SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;

}

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