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Exact meaning of MEM_PLL_RAT for LS102x products?

Question asked by Jean-Francois Riendeau on Dec 5, 2017
Latest reply on Dec 6, 2017 by Serguei Podiatchev

In the "QorIQ LS1021A Reference Manual, Rev. 2 04/2017", MEM_PLL_RAT is described as:

Memory controller complex PLL multiplier/ratio
This field configures the DDR PLL:SYSCLK ratio.

However, the "AN4878: QorIQ LS1021A Design Checklist, Rev. 4, 07/2017" is instead referring to "DDR data rate to DDRCLK" ratio:

In asynchronous DDR mode, the DDR data rate to DDRCLK ratios supported are listed in Table 66. This ratio is determined by the binary value of the RCW configuration field MEM_PLL_RAT (bits 10-15).

Then Table 66 lists the binary values of MEM_PLL_RAT to encode ratios between 6:1 and 24:1, which just happens to be the value on the left side of the ':'. Table 71 confirms this by listing the expected frequency options for DDRCLK and data rate.

 

So one document describes MEM_PLL_RAT as the ratio between DDR PLL and SYSCLK (i.e. frequency multiplier), while the other doesn't mention MEM_PLL_RAT per se, but describes a ratio between DDR data rate to DDRCLK. This is very confusing because DDR means "Double Data Rate", so the effective rate would double the frequency at which it runs.

 

Which one is right? And if I wanted to use a LS1022A, which only supports a DDR date rate of 1000MT/s, what value of MEM_PLL_RAT would I need in my RCW?

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