I'm trying to use the DDR validation suite in QCVS to get optimal values for WRLVL registers for our custom board. We have the u-boot loading, but it fails to detect the DIMM capacity of channel 1 of 1st and 2nd memory controllers. I'm able to connect to the target and import the settings from the target as well. But the validation fails with "error: endianness". I have tried starting with Auto configuration and Import from Target configuration. udimm part is Mircon, MTA9ASF1G72AZ.
Sometimes I can get past the endianness error; but validation fails before the final step with some "internal error".
Reading from SPD also fails in the DDRv tool. Please see attached pictures. I have also attached the u-boot log for reference.
Can someone help me with these errors, please?