I want to make a shared memory between linux (core0) and my bare metal (Core1) system. It works if I configure the mmu_map_l1_range in the mmu.c in my bare metal system as noncacheable! If I try to change the settings to kOuterInner_WB_WA and I activated SCU (also on CP15) because I want to use cache coherency it doesn’t work anymore! I only modified the MMU TLB setting on my bare metal system. Do I need to change also settings on the linux side to achieve cache coherency for the shared memory area.
Thank you in advance!