I'm using a T2080 processor with 0x66 SERDES configuration on SD1 bloc.
So, I have four "10 Gigabit ports" : two used in XFI mode, connected to Ethernet PHYs for 10GBASE-T support, and two directly connected to a backplane's interface.
The two Ethernet PHYs are connected to the EMI2 bus for configuration. They are using 0x0 and 0x1 addresses and respond without issue to all mdc/mdio commands.
I'd like to access to the T2080's MDIO register spaces to have information about processor's PCS and auto-negociation.
So, I have defined four new addresses, one for each port's MAC, assigning 0x2 to 0x5 into each MDEV_PORT field (in E_A6C4, E_A6D4, E_A6E4 and E_A6F4 : XFIx Protocol Control Register 1) .
Nevertheless, I cannot acces to MAC MDIO register spaces after this configuration : all accesses always return 0xffff.
=> Which configuration should be performed to access to these registers ?