I am trying to figure out the address decoding of a 8Gbit micron DDR3 RAM(with 8 logical banks) device.The datasheet mentions that 16 bits are used for row address and 10 bits are used for column address. According to the given information, the size of a single bank will be 2^16 (rows) * 2^7 (columns). Why is there another x128 mentioned in the block diagram?
Please find the attached image for your information. Thank you!