1. From the LS1046ARM Table 31-1, the SerDes 1 C(SD1_RX1/TX1) and D(SD1_RX0/TX0) should support XFI.But, in the PCCRB register fields, it shows Lane 2 and Lane 3 to XGMII, I am confused about what the Lane 2 and Lane 3 should refer to, the D1_RX0/TX0 and D1_RX1/TX1 or SD1_RX2/TX2 and SD1_RX3/TX3? otherwise,it is a misprint?
2. How can I access the PCCRB? when I used devmem 0x1EA022C on LS1046ARDB, it returned the value 0x00000021 which mismatched the fields description even if did endian swap.