I am using DSPI4 as SPI master. All SPI communication seems to work fine. Writing/reading is successfully executed but with occasional missing RX Frames that is causing my switch confioguration to fail.
My SPI configuration is 8-bits /frame, continuous, DSPI_USING_INTERRUPT (I used this because there is already interrupt handlers available in the sample project, etc).
I am chasing this problem wherein I can see that slave is sending complete frames from logic analyzer but the SPI master (MPC5748G) is not capturing all of it. So I dig a little deeper and I found a few things.
- DSPI_GET_SR_RXCTR does not provide the correct number of filled RX_FIFO, register value checked from Memory Windows is different than the one returned via call.
- The counter gets cleared even without using the DSPI_GET_POPR_RXDATA.
- the POPR register does not contain the data pointed by the POPNXTPTR
- Clearing FIFO via DSPI_SET_MCR_CLR_RXF does not clears the content of the FIFO as seen from the Memory Window.
Is there any known issue regarding DSPI RX_FIFO in MPC5748G, or is there anything I am misunderstanding here?
I've attached screenshot. I am hoping to get an answer if this is a known issue so I could stop investigating. Also please if there is a known work-around to address this issue if exist.
I need to do a lot of SPI writes , then SPI read at the end. It can't be a SPI WRITE = SPI READ, it can't be done this way in case of overflow/underflow situation as replied in other posted question. And even writing a one-to-one still seeing a lost frames. I really need to make decision urgently if this is worth my time and if we need to switch to different processor/controller.