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MCF54416 PLL does not lock

Question asked by Klaus Immig on Nov 17, 2017
Latest reply on Nov 2, 2018 by Klaus Immig

We are trying to boot our custom board (MCF54416) with the following options:

50 MHz external Reference, oscillator bypass, pll on, pll=10x fref.

 

First we try to boot with bootmode=01: RCON override with 0x2F but ~RSTOUT remains low.

We can see the FB_CLK running at 62.5MHz as expected.

 

The we try the same configuration with bootmode=11: override value for RCON = 0xA709FC61

We also try lower bus clock for fsys and fsys/2.

But the result is similar to the first attempt.

 

 

The only way to get the board into the "run" state:

 

  1. Power on reset with bootmode=11 (serial boot) without any serial device attached

            (this puts the oscillator in bypass mode)

  1. Trigger the external reset

            ( change reset cause from "POR" to "external reset")

  1. Changing the bootmode on the fly to "01" after ~RESET is deasserted

            (load all other RCON bit except oscillator mode)

After that the ~RSTOUT is released and the board can be accessed.

 

We have build several boards with the coldfire V2 so far.

So we carefuly check power supplies, clock reference and power up sequence.

All parameter seem to meet the requirements.

Are there any issues known which can cause such a behavior?

 

After some further testing we added a FRAM for serial boot.

Writing a configuration with oscillator bypass and PLL enabled result in an unlock state. The only way

to get it work is to start in LIMP mode. After ~RSTOUT is deasserted clock divider and PLL mode were set via software.

Before we could leave limp mode we have to add a small delay (1ms). After that a lock is achieved after the documented time elapsed (< 50ms).

 

Any suggestions?

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