LS1021A 1588 for Packet Generation and Parsing

[bengisu]

Hi,

I want to design a board with 1588 support. I use LS1021A with ethernet transceiver with a 1588 time stamping support. In this case, it is my understanding that LS1021A has to do only 1588 packet generation and parsing. In the reference manual, it is stated that 1588 registers are in eTEC1 memory space. Like my case when you do not need to timestamp 1588 packets in LS1021A, it is still necessary to enable eTEC1?1588 registers are only timestamp related or they are also necessary for 1588 packet issues? In my case because of IO muxing, I wan to use only eTEC2 & 3.

Thanks for any help.

Regards,

[r8070z]

Have a great day,

Support for 1588 can be done even in software running on a host CPU. Typically applications that require sub 10 μs accuracy need hardware support for accurate time stamping of incoming packets. You may use Ethernet transceiver with a 1588 time stamping support instead of the 1588 timer hardware which is available through registers mapped into TSEC1 address region. In this case you do not need to enable eTEC1.

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