AnsweredAssumed Answered

Setting EIM clock on 7D

Question asked by jayakumar2 on Nov 14, 2017
Latest reply on Nov 27, 2017 by jayakumar2


I'm using a 7D board with a EIM interface to an FPGA. I have this working well with 6sl using 66MHz clock. On 7d, I tried to setup the 66MHz clock using devicetree as per below:

&weim {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_weim_cs2_1>;
#address-cells = <2>;
#size-cells = <1>;
/* <cs-number> 0 <physical address of mapping> <size> */
ranges = <0 0 0x28000000 0x02000000>, /* 32MB CS0 */
<1 0 0x2A000000 0x02000000>, /* 32MB CS1 */
<2 0 0x2C000000 0x02000000>, /* 32MB CS2 */
<3 0 0x2E000000 0x02000000>; /* 32MB CS3 */
status = "okay";
fsl,weim-cs-gpr = <&gpr>;
assigned-clock-rates = <66000000>;

imx-weim@2,0 {
compatible = "fsl,imx6q-weim";
reg = <2 0 0x02000000>;
#address-cells = <1>;
#size-cells = <1>;
bank-width = <2>;

fsl,weim-cs-timing = <0x00e10089 0x00001130 0x01010000 0x00000000 0x06040600 0x00000000>;

imx-weim@3,0 {
compatible = "fsl,imx6q-weim";
reg = <3 0 0x02000000>;
#address-cells = <1>;
#size-cells = <1>;
bank-width = <2>;
fsl,weim-cs-timing = <0x00e10089 0x00001130 0x02010000 0x00000000 0x06040600 0x00000000>;


The processing of that looks fine. I dumped the EIM_CS3/4 regs and they match the configuration values specified above. When I access the memory space, I get CS assertion and the transaction (aside from exact timing) looks reasonable.


The part that does not seem to work is the assigned-clock-rate. I've specified 66MHz above. But it does not seem to have any effect on the physical interface. Here's the timing that I get:

7d eim timing

D15 is the chipselect. D11-D0 are address lines.

The total chipselect assertion time is only 65ns which is only 4 clocks at 66MHz! It should be about 350ns (which is what it is on 6sl).

Signals like LBA and Address phase seem out of sync (LBA gets asserted before address seems to be valid). This leads to me think that the core EIM clock is wrong.

imx7d.dtsi says:

weim: weim@30bc0000 {
compatible = "fsl,imx7d-weim", "fsl,imx6sx-weim", "fsl,imx6q-weim";
reg = <0x30bc0000 0x10000>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7D_EIM_ROOT_CLK>;
status = "disabled";


I checked that the assigned clock rate seems to match what I set:

root@imx7dsabresd:~# hexdump -C /sys/firmware/devicetree/base/soc/aips-bus\@30800000/weim\@30bc0000/assigned-clock-rates
00000000 03 ef 14 80 |....|

root@imx7dsabresd:~# printf %d, 0x3ef1480


Is there a step or parameter that I have missed in order to setup the EIM clock.


I would welcome any advice or suggestions.