i'd like to use the Time Base registers to capture time in my software.
i'm using the HID0[SEL_TBCLK]=0 so the TB is updated every 8 core complex bus (CCB) clocks.
my question is : How can i read the TBU and TBL at the same time so i have a good correlation between the 2 registers value ?
Some processors i worked with have some kind of freezing mechanism, but i don't see anything like like for the P2020.
in §4.7.3, the EREF_RM describes a 64-bit mode for spr 268 (TBL) in order to read the TB. Is it possible on P2020 ?