I am trying to configure the DDR Memory Controller registers of T1042. While configuring the DDR_SDRAM_MODE register i found that that DDR_SDRAM_MODE [WR] field (bit number 20-22 of the register) should be given the same value as assigned to the field WRREC in the TIMING_CFG_1 register. The confusion here is that WRREC field in the TIMING_CFG_1 register is of 4 bits whereas the WR field in DDR_SDRAM_MODE register is of 3 bits. I want to configure it to "15 cycles" that require 4 bits. Please guide me how can i achieve that?
Please find the attached manual for information. Thank you!