I’m hoping you can help us on a problem we are having with trying to use SDRAM on the K66. We have some example code from a K65 reference board and an appnote on how to configure the SDRAM controller that we are following. I am able to see the bus activity with a logic analyzer, and while I see precharge and refresh cycles, the code to set the mode register and read or write produces no bus activity. It seems like there is another setting somewhere that is blocking the SDRAM controller from accessing the SDRAM. Do you have any ideas on this?
Last night I found this in the K66 manual:
9.3.1 Security interactions with FlexBus and SDRAM controller
When flash security is enabled, SIM_SOPT2[FBSL] enables/disables off-chip accesses
through the FlexBus and the SDRAM interfaces. The FBSL bitfield also has an option to
allow opcode and operand accesses or only operand accesses.
There is also this warning in the description of the FBSL bits in the SIM_OPT2 register:
FlexBus security level
If flash security is enabled, then this field affects what CPU operations can access off-chip via the
FlexBus or SDRAMinterface. This field has no effect if flash security is not enabled.
00 All off-chip accesses (instruction and data) via the FlexBus or SDRAM are disallowed.
01 All off-chip accesses (instruction and data) via the FlexBus or SDRAM are disallowed.
10 Off-chip instruction accesses are disallowed. Data accesses are allowed.
11 Off-chip instruction accesses and data accesses are allowed.
I looked through the K66 manual to find that the flash security bits live in the FTFE_FSEC register. I read this register in our code and found that the SEC bits (1-0) are 10b which is the unsecure state. So is it reasonable that since the flash security is not enabled, then the SIM_OPT2(FBSL) bits have no effect and there can be no bus accesses by the SDRAM controller?
To complicate matters, the FTFE_FSEC register is read-only and gets it's contents from the flash security byte in the Flash Configuration Field in the flash program memory (from pg 748 of the K66 Ref manual). How then can I enable the SDRAM controller? Compiler switch for code security? We are using IAR workbench.
Does this make any sense at all?