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about i.MX6 PCIe cache coherency

Question asked by Masami Yasui on Nov 8, 2017
Latest reply on Nov 8, 2017 by Masami Yasui

In i.MX6Q PCIe End Point,  if cache is enabled  in the inbound area, I think that cache invalidate is necessary before and after writing from Root Complex to this area.
How can End Point know the timing of these cache invalidate?

Without these cache invalidate, End Point could not read the data which Root Complex wrote to this area.

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