In the K66 and K65 MCUs, how does a 32bit address in an instruction get translated to the SDRAM controller address pins A23-A9?
As you know that the SDRAM is connected to K65/66 via SDRAM controller, the SDRAM controller can generate the corresponding Column address and Row address to access SDRAM if the space is in the SDRAM range. For K65, the 0x8000_0000–0x8FFF_FFFF is SDRAM address space, after the SDRAM is initialized, when you access the above space, the SDRAM will generate the timing to access SDRAM, you can access the SDRAM as you access the internal SRAM, you do not need consider the precharge/activate/refresh...
I do not know if you ask the connection between SDRAM and SDRAM controller, based on SDRAM chip column address and data width(32 bits/16 bits/8 bits), the K65 provides several tables, which tell you how to connect the address between SDRAM controller address and SDRAM address.
Hope it can help you
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