I am not clear about the 24 bit SPWG/PSWG/VESA data mapping given in imx6 technical reference manual section 39.5.2. In below table 39.6, R6,G6,B6 represents LSB color bit or 6th color bits ? ( when BIT_MAPPING_CH0 = 0 ,SPWG and DATA_WIDTH_CH0=1, 24 bit)
I am trying to interface 2 different 24 bit parallel RGB display with imx6 using LVDS0 port with Ti's deserilizer chip, DS90CF384A. In the below figure (table 1) R6 is LSB , R7 is LSB +1 , R0 is LSB+2 ,... and R5 is MSB and it is similar for Green and Blue data.
By comparing deserializer chip mapping and imx6 bit mapping, the data coming out of imx6 at LVDSn_DATA3 lane ( B6 B7 G6 G7 R6 R7 ) should be LSB in 24 bit map. is this correct?
If i considered the data coming out of imx6 at LVDSn_DATA3 lane (B6 B7 G6 G7 R6 R7 ) as MSB bits, one display is working properly and another 24 bit display doesn't work in this mapping ( corrupted colors)
if I considered those data as LSB as per deserilizer chip both displays images are not proper. can anyone confirm iMX6 side data mapping properly for 18 bit mode and 24 bit mode? Particularly for LVDSn_DATA3 lane.