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T4241 PCI Scan

Question asked by senthilkumarg on Nov 6, 2017

In our custom T4241 board, we connected PCIe switch to PCIe Controller 1(Root complex) as X8 interface. In U-boot on PCI scan, the bridge is identified. But other two pcie devices connected in switch is not connected. We expected In Bus 0, the root complex T4241 PCI information to be displayed but it is displaying switch information.

 

Any configuration to be done in u-boot to scan and allocate the memory for device connected beyond the switch.

=> pci 0
Scanning PCI devices on bus 0
BusDevFun VendorId DeviceId Device Class Sub-Class
_____________________________________________________________
00.02.00 0x111d 0x807a Bridge device 0x04
00.04.00 0x111d 0x807a Bridge device 0x04
00.06.00 0x111d 0x807a Bridge device 0x04
00.07.00 0x111d 0x807a Bridge device 0x04
00.08.00 0x111d 0x807a Bridge device 0x04
00.09.00 0x111d 0x807a Bridge device 0x04
00.0c.00 0x111d 0x807a Bridge device 0x04
00.0d.00 0x111d 0x807a Bridge device 0x04
=> pci h 0.0.0
vendor ID = 0x111d
device ID = 0x807a
command register ID = 0x0007
status register = 0x0010
revision ID = 0x02
class code = 0x06 (Bridge device)
sub class code = 0x04
programming interface = 0x00
cache line = 0x08
latency time = 0x00
header type = 0x01
BIST = 0x00
base address 0 = 0x00000000
base address 1 = 0x00000000
primary bus number = 0xff
secondary bus number = 0x00
subordinate bus number = 0x08
secondary latency timer = 0x00
IO base = 0x01
IO limit = 0x11
secondary status = 0x0000
memory base = 0x0000
memory limit = 0xe100
prefetch memory base = 0x1e11
prefetch memory limit = 0x0001
prefetch memory base upper = 0xffff0000
prefetch memory limit upper = 0x00000000
IO base upper 16 bits = 0x0000
IO limit upper 16 bits = 0x0000
expansion ROM base address = 0x00000000
interrupt line = 0x00
interrupt pin = 0x00
bridge control = 0x0000
=>

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