AnsweredAssumed Answered

ADC0_CH7 and ADC0_CH8 triggle dma request question in mpc574x

Question asked by 大大 许 on Nov 5, 2017
Latest reply on Nov 19, 2017 by 大大 许

Hi dear,

I have some question about ADC0_CH7 and ADC0_CH8 triggle dma request question in mpc574x. In my test,I try using ADC0_Ch7 and ADC0_CH8 EOC condition to triggle DAM transfer,pushing ADC0CH7 and ADC0CH8 CDR  regist's result to indicate data buffer. But in my test, I find only one channel result is true ,other channel result in bad data. How should i change my configure to make ADC0_CH7 and CH8 transfer data is right. DMA use fix_prio and ADC0_CH7 prio == 7, ADC0_CH8 prio == 8

follow is my configure

ADC_0.DMAR0.B.DMA8 = 1;   
 ADC_0.DMAR0.B.DMA7 = 1;
 ADC_0.DMAE.B.DCLR = 0; 
 ADC_0.DMAE.B.DMAEN = 1;  

 

DMA_0.CR.B.CX = 0;      //normal operate mode
 DMA_0.CR.B.ECX = 0;
 DMA_0.CR.B.GRP1PRI = 1;    //Fixed priority arbitration
 DMA_0.CR.B.GRP0PRI = 0;
 DMA_0.CR.B.EMLM = 1;      //enable minor loop mapping and disable offset
 DMA_0.CR.B.CLM = 0;
 DMA_0.CR.B.HALT = 0;
 DMA_0.CR.B.HOE = 0;
 DMA_0.CR.B.ERGA = 0; 
 DMA_0.CR.B.ERCA = 0;
 DMA_0.CR.B.EDBG = 0;

 

DMAMUX_0.CHCFG[4].B.TRIG = 0;             //设置adc0_ch8的dma通道
 DMAMUX_0.CHCFG[4].B.SOURCE = 0x12;
 DMAMUX_0.CHCFG[4].B.ENBL = 1;

 DMA_0.ERQ.B.ERQ4 = 1; //open hardware request
 
 DMA_0.TCD[4].SADDR.R = 0xFBE00120;   //ADC0_CH8_CDR_ADD
    DMA_0.TCD[4].ATTR.B.SMOD = 0;  
    DMA_0.TCD[4].ATTR.B.SSIZE = 2;       //uint16  
  DMA_0.TCD[4].SOFF.R = 0;   
 DMA_0.TCD[4].SLAST.R = 0;

 DMA_0.TCD[4].DADDR.R =(uint32_t) adc0Ch8Data;            
 DMA_0.TCD[4].ATTR.B.DMOD = 0;
 DMA_0.TCD[4].ATTR.B.DSIZE = 2;
 DMA_0.TCD[4].DOFF.R = 4;
 DMA_0.TCD[4].DLASTSGA.R = -80;       //只有在major loop 完成以后才执行这个步骤

 DMA_0.TCD[4].NBYTES.MLOFFNO.B.SMLOE = 0;   //minor loop enable and link-to-link disable
 DMA_0.TCD[4].NBYTES.MLOFFNO.B.DMLOE = 0;   //minor loop offset is applied to the SADDR
 DMA_0.TCD[4].NBYTES.MLOFFNO.B.NBYTES = 4;           //minor loop cnt 
 DMA_0.TCD[4].BITER.ELINKNO.B.ELINK = 0;    
 DMA_0.TCD[4].BITER.ELINKNO.B.BITER = 20;    
 DMA_0.TCD[4].CITER.ELINKNO.B.ELINK = 0;
 DMA_0.TCD[4].CITER.ELINKNO.B.CITER = 20; 
 DMA_0.TCD[4].CSR.B.BWC = 0;
 DMA_0.TCD[4].CSR.B.MAJORLINKCH = 0;
 DMA_0.TCD[4].CSR.B.ACTIVE = 0;
 DMA_0.TCD[4].CSR.B.DONE = 0;
 DMA_0.TCD[4].CSR.B.MAJORELINK = 0;
 DMA_0.TCD[4].CSR.B.ESG = 0;
 DMA_0.TCD[4].CSR.B.INTHALF = 0;
 DMA_0.TCD[4].CSR.B.INTMAJOR = 1;
 DMA_0.TCD[4].CSR.B.START = 0;

DMAMUX_0.CHCFG[5].B.TRIG = 0;             //设置adc0_ch7的dma通道
 DMAMUX_0.CHCFG[5].B.SOURCE = 0x12;
 DMAMUX_0.CHCFG[5].B.ENBL = 1;
 DMA_0.ERQ.B.ERQ5 = 1; //open hardware request
 DMA_0.TCD[5].SADDR.R = 0xFBE0011C;   //ADC0_CH7_CDR_ADD
    DMA_0.TCD[5].ATTR.B.SMOD = 0;  
    DMA_0.TCD[5].ATTR.B.SSIZE = 2;       //uint16  
  DMA_0.TCD[5].SOFF.R = 0;   
 DMA_0.TCD[5].SLAST.R = 0;
 DMA_0.TCD[5].DADDR.R =(uint32_t) adc0Ch7Data;            
 DMA_0.TCD[5].ATTR.B.DMOD = 0;
 DMA_0.TCD[5].ATTR.B.DSIZE = 2;
 DMA_0.TCD[5].DOFF.R = 4;
 DMA_0.TCD[5].DLASTSGA.R = -80;       //只有在major loop 完成以后才执行这个步骤
 DMA_0.TCD[5].NBYTES.MLOFFNO.B.SMLOE = 0;   //minor loop enable and link-to-link disable
 DMA_0.TCD[5].NBYTES.MLOFFNO.B.DMLOE = 0;   //minor loop offset is applied to the SADDR
 DMA_0.TCD[5].NBYTES.MLOFFNO.B.NBYTES = 4;           //minor loop cnt
 DMA_0.TCD[5].BITER.ELINKNO.B.ELINK = 0;    
 DMA_0.TCD[5].BITER.ELINKNO.B.BITER = 20;    
 DMA_0.TCD[5].CITER.ELINKNO.B.ELINK = 0;
 DMA_0.TCD[5].CITER.ELINKNO.B.CITER = 20; 
 DMA_0.TCD[5].CSR.B.BWC = 0;
 DMA_0.TCD[5].CSR.B.MAJORLINKCH = 0;
 DMA_0.TCD[5].CSR.B.ACTIVE = 0;
 DMA_0.TCD[5].CSR.B.DONE = 0;
 DMA_0.TCD[5].CSR.B.MAJORELINK = 0;
 DMA_0.TCD[5].CSR.B.ESG = 0;
 DMA_0.TCD[5].CSR.B.INTHALF = 0;
 DMA_0.TCD[5].CSR.B.INTMAJOR = 1;
 DMA_0.TCD[5].CSR.B.START = 0;

Thanks!

Outcomes