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connect P1010 with code warrior10.5

Question asked by 慕晗 潘 on Nov 4, 2017
Latest reply on Dec 3, 2017 by Yiping Wang

Using Code Warrior 10.5 to connect the P1010, but failed.

Error : ELF is not in expected HALT mode

I use "P1010RDB_init_sram.tcl" to Initize P1010.

I need help, thanks.

ELF is not in expected HALT mode

 

following is "P1010RDB_init_sram.tcl"

#########################################################################
# Initialization file for P1010RDB board - SRAM
# Clock Configuration:
# CPU: 1000 MHz, CCB: 400 MHz,
# DDR: 800 MHz, SYSCLK: 100 MHz
#########################################################################

variable CCSRBAR 0xff700000

proc CCSR {reg_off} {
global CCSRBAR

return p:0x[format %x [expr {$CCSRBAR + $reg_off}]]
}

proc apply_e500v2_workaround {} {
# After reset, e500 cores need to run before being able to enter debug mode.
# Work-around: set a HW BP at reset address and run the core; after the core hits the BP, it enters debug mode
# e500 cores need to have valid opcode at the interrupt vector

variable SPR_GROUP "e500 Special Purpose Registers/"
variable GPR_GROUP "General Purpose Registers/"
#######################################################################
# Set a breakpoint at the reset address
reg ${SPR_GROUP}IAC1 = 0xfffffffc
reg ${SPR_GROUP}DBCR0 = 0x40800000
reg ${SPR_GROUP}DBCR1 = 0x00000000

# Run the core
config runcontrolsync off
protocol ccs::run_core 0
wait 500
protocol ccs::stop_core 0
config runcontrolsync on
stop

# Clear affected registers
reg ${SPR_GROUP}DBSR = 0x01CF0000
reg ${SPR_GROUP}DBCR0 = 0x41000000
reg ${SPR_GROUP}IAC1 = 0x00000000
reg ${SPR_GROUP}CSRR0 = 0x00000000
reg ${SPR_GROUP}CSRR1 = 0x00000000
# Set the PC back to the reset address (for debug-->connect)
reg ${GPR_GROUP}PC = 0xfffffffc
}

proc init_board {} {

global CCSRBAR

# get ROM_LOC from PORBMSR
variable ROM_LOC 0x[format %x [expr {([mem [CCSR 0xE0004] -np] & 0x0f000000) >> 24}]]

##################################################################################
# configure internal SRAM at 0x00000000

# L2CTL
# bit 0 = 0 - L2E: L2 SRAM disabled
# bit 1 = 1 - L2I: L2 flash invalidate
# bit 2-3 = 01 - L2SIZ: = 256K
# bit 13-15 = 001 - L2SRAM: Entire array as SRAM (256K)
mem [CCSR 0x20000] = 0x50010000


# L2SRBAR0
# bit 0-17 = BASE addr: 0x00000000
mem [CCSR 0x20100] = 0x00000000

# L2SRBAREA0
# bit 28-31 = EXTENTED BASE addr: 0x00000000
mem [CCSR 0x20104] = 0x00000000

# L2CTL
# bit 0 = 1 - L2E: L2 SRAM enable
mem [CCSR 0x20000] = 0x90010000

##################################################################################
#
# Memory Windows
#
# 0xFE000000 0xFFFFFFFF LAW0 Local Bus NOR FLASH - 32M
# 0xEFB00000 0xEFBFFFFF LAW1 CPLD - 128K
# 0xEFA00000 0xEFAFFFFF LAW2 NAND - 16k
#
##################################################################################
# configure local access windows

# LAWBAR0 - IFC
# bit 8 - 31 = 0xFE000000 - base addr
mem [CCSR 0xC08] = 0x000fe000

# LAWAR0
# bit 0 = 1 - enable window
# bit 7-11 = 00100 - Local Bus
# bit 26 - 31 = 011000 32M - size
mem [CCSR 0xC10] = 0x80400018

# LAWBAR1 - CPLD
# bit 8 - 31 = 0xEFB00000 - base addr
mem [CCSR 0xC28] = 0x000efb00

# LAWAR1
# bit 0 = 1 - enable window
# bit 7-11 = 00100 - Local Bus
# bit 26-31 = 010000 128k - size
mem [CCSR 0xC30] = 0x80400010

# LAWBAR2 - Local Bus
# bit 8 - 31 = 0xEFA00000 - base addr
mem [CCSR 0xC48] = 0x00efa00

# LAWAR2
# bit 0 = 1 - enable window
# bit 7-11 = 00100 - IFC
# bit 26-31 = 010011 1M - size
mem [CCSR 0xC50] = 0x80400013

#######################################
# CPLD INIT
#######################################

config MemAccess 8
config MemWidth 8
mem v:0xefb00009 = 0x00
mem v:0xefb00013 = 0x00
config MemAccess 32
config MemWidth 32

##################################################################################
# added workaround for Errata ID - GEN-A016 (A-003549)
# PMUXCR
mem [CCSR 0xE0060] = 0x000000c0

##################################################################################
# configure IFC controller

# Autodetect CS routing based on ROM_LOC
# bits 4-7 - ROM_LOC
# 1000 8-bit NAND—512b page size
# 1001 8-bit NAND—2K page size
# 1010 8-bit NAND—4K page size
# 1011 8-bit NOR
# 1100 16-bit NAND—512b page size
# 1101 16-bit NAND—2K page size
# 1110 16-bit NAND—4K page size
# 1111 16b NOR

# boot location is NAND => NAND - cS0, NOR - CS1
if {($ROM_LOC >= 0x8 && $ROM_LOC <= 0xA) || (($ROM_LOC >= 0xC && $ROM_LOC <= 0xE))} {

###########################
# CS0 - NAND Flash settings

# AMASK0 64k NAND Flash buffer size
mem [CCSR 0x1E0A0] = 0xFFFF0000

# CSOR0
mem [CCSR 0x1E130] = 0x0110A200

#FTIM0_CS0
mem [CCSR 0x1E1C0] = 0x0E18070A
#FTIM1_CS0
mem [CCSR 0x1E1C4] = 0x32390E18
#FTIM2_CS0
mem [CCSR 0x1E1C8] = 0x01E0501E
#FTIM3_CS0
mem [CCSR 0x1E1CC] = 0x00000000

# CSPR0
mem [CCSR 0x1E010] = 0xEFA00083

##########################
# CS1 - NOR Flash settings

# AMASK1 32M NOR
mem [CCSR 0x1E0AC] = 0xFE000000

# CSOR1
mem [CCSR 0x1E13C] = 0x0000E000

#FTIM0_CS1
mem [CCSR 0x1E1F0] = 0x40050005
#FTIM1_CS1
mem [CCSR 0x1E1F4] = 0x1E000F00
#FTIM2_CS1
mem [CCSR 0x1E1F8] = 0x0410001C
#FTIM3_CS1
mem [CCSR 0x1E1FC] = 0x00000000

# CSPR1
mem [CCSR 0x1E01C] = 0xFE000105

} else {

##########################
# CS0 - NOR Flash settings

# AMASK0 32M NOR
mem [CCSR 0x1E0A0] = 0xFE000000

# CSOR0
mem [CCSR 0x1E130] = 0x0000E000

#FTIM0_CS0
mem [CCSR 0x1E1C0] = 0x40050005
#FTIM1_CS0
mem [CCSR 0x1E1C4] = 0x1E000F00
#FTIM2_CS0
mem [CCSR 0x1E1C8] = 0x0410001C
#FTIM3_CS0
mem [CCSR 0x1E1CC] = 0x00000000


# CSPR0
mem [CCSR 0x1E010] = 0xFE000105

###########################
# CS1 - NAND Flash settings

# AMASK1 64k NAND Flash buffer size
mem [CCSR 0x1E0AC] = 0xFFFF0000

# CSOR1
mem [CCSR 0x1E13C] = 0x0110A200

#FTIM0_CS1
mem [CCSR 0x1E1F0] = 0x0E18070A
#FTIM1_CS1
mem [CCSR 0x1E1F4] = 0x32390E18
#FTIM2_CS1
mem [CCSR 0x1E1F8] = 0x01E0501E
#FTIM3_CS1
mem [CCSR 0x1E1FC] = 0x00000000

# CSPR1
mem [CCSR 0x1E01C] = 0xEFA00083
}

# CS3 - CPLD
#CSPR3 base address at 0xEFB00000, valid
mem [CCSR 0x1E034] = 0xEFB00085
#AMASK3 64K
mem [CCSR 0x1E0C4] = 0xFFFF0000
#CSOR3
mem [CCSR 0x1E154] = 0x00000000

#FTIM0_CS3
mem [CCSR 0x1E250] = 0xe00e000e
#FTIM1_CS3
mem [CCSR 0x1E254] = 0x0e001f00
#FTIM2_CS3
mem [CCSR 0x1E258] = 0x0e00001f
#FTIM3_CS3
mem [CCSR 0x1E25C] = 0x00000000

#GCR
mem [CCSR 0x1E40C] = 0x00002800
#CCR
mem [CCSR 0x1E44C] = 0x03008000


#SPI init
# SPMODE
mem [CCSR 0x7000] = 0x80000403
# SPIM - catch all events
mem [CCSR 0x7008] = 0x00000000
# SPMODE1
mem [CCSR 0x7020] = 0x28170008
}

proc P1010RDB_init_core {} {
global CCSRBAR

variable SPR_GROUP "e500 Special Purpose Registers/"
variable SSP_GROUP "Standard Special Purpose Registers/"
variable CAM_GROUP "regPPCTLB1/"
variable GPR_GROUP "General Purpose Registers/"

##################################################################################
# move CCSR at 0xE0000000

# CCSRBAR
# bit 8 - 23 - BASE_ADDR
mem [CCSR 0x0] = 0x000e0000
set CCSRBAR 0xe0000000

######################################################################
# invalidate BR0
# CSPR0
mem [CCSR 0x1E010] = 0x00000100

# ABIST off
# L2ERRDIS[MBECCDIS]=1 L2ERRDIS[SBECCDIS]=1
mem [CCSR 0x20E44] = 0x0000000C

# activate debug interrupt and enable SPU
reg ${SSP_GROUP}MSR = 0x02000200

##################################################################################
#
# Memory Map
#
# 0x00000000 0x0003FFFF SRAM 256K
# 0xE0000000 0xE00FFFFF CCSRBAR Space 1M
# 0xEFA00000 0xEFA03FFF NAND 16k
# 0xEFB00000 0xEFBFFFFF Board CPLD 1M
# 0xFE000000 0xFFFFFFFF LocalBus NOR FLASH 32M
#
##################################################################################
# MMU initialization

# define 16MB TLB entry 0: 0xFF000000 - 0xFFFFFFFF; for Local Bus, cache inhibited, guarded
reg ${CAM_GROUP}L2MMU_CAM0 = 0x70000FCAFC080000FF000000FF000001

# define 16MB TLB entry 1: 0xFE000000 - 0xFEFFFFFF; for Local Bus, cache inhibited, guarded
reg ${CAM_GROUP}L2MMU_CAM1 = 0x70000FCAFC080000FE000000FE000001

# define 1MB TLB entry 2: 0xE0000000 - 0xE00FFFFF; for CCSR Space, non cacheable
reg ${CAM_GROUP}L2MMU_CAM2 = 0x500003CAFC080000E0000000E0000001

# define 256KB TLB entry 3: 0x00000000 - 0x0003FFFF; for internal chip SRAM
reg ${CAM_GROUP}L2MMU_CAM3 = 0x400001C0FC0800000000000000000001

# define 256KB TLB1 entry 4: 0xEFB00000 - 0xEFB3FFFF; for CPLD, cache inhibited, guarded
reg ${CAM_GROUP}L2MMU_CAM4 = 0x400001CA1C080000EFB00000EFB00001

# define 1MB TLB1 entry 5: 0xEFA00000 - 0xEFAFFFF; for NAND cache inhibited, guarded
reg ${CAM_GROUP}L2MMU_CAM5 = 0x500003CA1C080000EFA00000EFA00001

##################################################################################
# disable Boot Page Translation Register
mem [CCSR 0x20] = 0x00000000

# Invalidate again CSPR0 to prevent flash data damage in case
# the boot sequencer re-enables CS0 access
mem [CCSR 0x1E010] = 0x00000100

init_board

####################################################################
# interrupt vectors initialization
# IVPR (default reset value)
reg ${SPR_GROUP}IVPR = 0x00000000

# interrupt vector offset registers
# IVOR0 - critical input
reg ${SPR_GROUP}IVOR0 = 0x00000100
# IVOR1 - machine check
reg ${SPR_GROUP}IVOR1 = 0x00000200
# IVOR2 - data storage
reg ${SPR_GROUP}IVOR2 = 0x00000300
# IVOR3 - instruction storage
reg ${SPR_GROUP}IVOR3 = 0x00000400
# IVOR4 - external input
reg ${SPR_GROUP}IVOR4 = 0x00000500
# IVOR5 - alignment
reg ${SPR_GROUP}IVOR5 = 0x00000600
# IVOR6 - program
reg ${SPR_GROUP}IVOR6 = 0x00000700
# IVOR8 - system call
reg ${SPR_GROUP}IVOR8 = 0x00000c00
# IVOR10 - decrementer
reg ${SPR_GROUP}IVOR10 = 0x00000900
# IVOR11 - fixed-interval timer interrupt
reg ${SPR_GROUP}IVOR11 = 0x00000f00
# IVOR12 - watchdog timer interrupt
reg ${SPR_GROUP}IVOR12 = 0x00000b00
# IVOR13 - data TLB errror
reg ${SPR_GROUP}IVOR13 = 0x00001100
# IVOR14 - instruction TLB error
reg ${SPR_GROUP}IVOR14 = 0x00001000
# IVOR15 - debug
reg ${SPR_GROUP}IVOR15 = 0x00001500
# IVOR32 - SPE-APU unavailable
reg ${SPR_GROUP}IVOR32 = 0x00001600
# IVOR33 - SPE-floating point data exception
reg ${SPR_GROUP}IVOR33 = 0x00001700
# IVOR34 - SPE-floating point round exception
reg ${SPR_GROUP}IVOR34 = 0x00001800
# IVOR35 - performance monitor
reg ${SPR_GROUP}IVOR35 = 0x00001900

# put a valid opcode at debug and program exception vector address
mem v:0x00000700 = 0x48000000
mem v:0x00001500 = 0x48000000

##################################################################################
apply_e500v2_workaround

#############
#
# activate debug interrupt and enable SPU
reg ${SSP_GROUP}MSR = 0x02001200

############
#
# time base enable & MAS7 update
# HID0
reg ${SPR_GROUP}HID0 = 0x00004080

######
# CW debugger settings
#
#Trap debug event enable
reg ${SPR_GROUP}DBCR0 = 0x41000000

# for debugging starting at program entry point when stack is not initialized
reg ${GPR_GROUP}SP = 0x0000000F
}

proc envsetup {} {
# Environment Setup
radix x
config hexprefix 0x
config MemIdentifier v
config MemWidth 32
config MemAccess 32
config MemSwap off
}

#-------------------------------------------------------------------------------
# Main
#-------------------------------------------------------------------------------

envsetup

P1010RDB_init_core

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