MD SD

ADC16 Asynch clock Information

Discussion created by MD SD on Nov 5, 2017
Latest reply on Nov 9, 2017 by xiangjun.rong

Hi,

 

I am using MKL17Z32VFM4, ADC in 16bits diff mode, triggered with TPM at constant frequency for several samples (about 10). So first sample have the same given time with TPM than next ones. I want to optimize speed to decrease consumption, and also want low noise.

 

For noise, I am willing to use the asynk clock, but I cant find the necessary information ...
How do this clock work ? I see how to enable it, I see it connection on the Block diagram, but without any input for clk ? what frequency is it?
Is there a reel difference for noise compared to normal clock ? as on "Typical ENOB vs. ADC_CLK for 16-bit differential mode" it the graph goes up to 12Mhz, and at the same time for asynk clock, it is specified 9.5Mhz max.

 

In the Manuel for ADACKEN, it is written : "Also, latency of initiating a single or first-continuous conversion with the asynchronous clock selected is reduced because the ADACK clock is already operational."
What latency will have the first samples with/without ADACKEN ? Especially regarding sample.

 

Thanks,
Matt

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