i.MX25 wake on FEC interrupt (from stop mode) possible?

[stephenbialkows]

Hello,

Our target wakes on the FEC interrupt when returning from wait mode.  We would it to wake on FEC interrupt from stop mode.  This doesn't seem to work.  After reviewing the RM, I believe this is because the AHB bus clocks are off. 

The FEC has two clocks enabled by default (AHB and IPG).  I'm having a hard time understanding what the IPG bus is.  My motivation is to configure the IP bus such that we can wake on an FEC interrupt in stop mode.  Is this possible? 

Thanks!

Stephen

P.S. An image of the iMX25 clock tree will be worth it's weight in gold!

[Yuri · Accepted solution]

Hello,

   In Stop mode—all PLLs and all clocks are shut down. FEC does not have special

(static or 32KHz ) wake up option.

Have a great day,
Yuri

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

[stephenbialkows]

Yuri,

Thanks for your prompt reply.  Is it possible to wake from DOZE mode via an FEC interrupt?  It didn't appear to work after setting the bits in the clock gating control registers for hclk_fec and ipg_clk_fec. 

[Yuri]

Hello,

  In Doze mode  ARM platform clock is off and all the other modules are off,

this means FEC interrupts cannot be served (as wake up events). 

  Wait mode can be used with FEC interrupts (as wake up events).

Regards,

Yuri.

[stephenbialkows]

Yuri,

Thanks for that clarification.  I need to be able to explain why the FEC interrupt cannot wake the core from Doze mode in more detail.  Please forgive my persistence. 

The platform clock is certainly off in Doze mode.  According to table 8-1 in the reference manual, "all other modules are optionally disabled" for Doze mode. Are we referring to the same document (i.MX25 reference manual)?

Here is what I understand.  Perhaps you will be kind enough to help me fill in the blanks, and confirm/reject the following. 

• The PHY is always powered.  The PHY provides the RMII 50MHz ref clock to the FEC. 
• Figure 1-1 shows the FEC interfaces through the EMI/SDMA subsystem (not the ARM9 platform subsystem). I can't find anything that clarifies how the FEC communicates via EMI and/or SDMA.  Although, the FEC interrupt assertion from the perspective of the ASIC may be entirely irrelevant.  But, I have to suspect at some level that if FEC <--> EMI/SDMA clocks are un-gated, and thus working, so should be working the IRQ wake.
• Section 15.4.3.2.3 Doze Mode of the reference manual reads, "In doze mode the processor and MAX clocks are gated.  The clock source is still available, and peripherals that do not require MAX and core functionality can be active".  Yes, MAX clocks are unconditionally gated.  But, I think this means the SDMA clock doesn't have to be gated in doze mode.  True or false? 
• Although the ASIC is part of the ARM9 platform (wherein platform clocks are disabled during Doze mode), interrupts are dispatched to the ASIC outside the platform, and can wake the platform from Doze and Stop modes.  At least I know this is the case with GPIO interrupts.  Chapter 27 mentions a interrupt control unit in the GPIO modules.  It says nothing about clock considerations.  And thus, there is nothing to lead me to believe this special wake hardware. 

This information, alone, doesn't tell me why FEC interrupts "cannot be served (as wake up events)".  Perhaps you will be kind enough to help me fill in the blanks.  

Thanks,

Stephen

[Yuri]

Hello,

1.

  Correct, if FEC module clocks are not gated, assuming FEC is working in DOZE mode, its interrupts can

be used for wake up.

2.

  Note, although FEC is shown on Figure 1-1 as SDMA peripherals, this only means, that in general SDMA

can serve FEC requests. But FEC has own DMA , that is more effective.

Regards,

Yuri.