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linux pcie dts

Question asked by shunping lin on Nov 1, 2017
Latest reply on Nov 2, 2017 by shunping lin

Now I have a problem about pcie dts. In ls1021a.dtsi, have a pcie description:

pcie@3400000 {
                        compatible = "fsl,ls1021a-pcie", "snps,dw-pcie";
                        reg = <0x00 0x03400000 0x0 0x00010000   /* controller registers */
                               0x40 0x00000000 0x0 0x00002000>; /* configuration space */
                        reg-names = "regs", "config";
                        interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
                        interrupt-names = "pme", "aer";
                        fsl,pcie-scfg = <&scfg 0>;
                        #address-cells = <3>;
                        #size-cells = <2>;
                        device_type = "pci";
                        num-lanes = <4>;
                        bus-range = <0x0 0xff>;
                        ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
                                  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
                        msi-parent = <&msi>;
                        #interrupt-cells = <1>;
                        interrupt-map-mask = <0 0 0 7>;
                        interrupt-map = <0000 0 0 1 &gic GIC_SPI 91  IRQ_TYPE_LEVEL_HIGH>,
                                        <0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
                                        <0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
                                        <0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
                };

 

                pcie@3500000 {
                        compatible = "fsl,ls1021a-pcie", "snps,dw-pcie";
                        reg = <0x00 0x03500000 0x0 0x00010000   /* controller registers */
                               0x48 0x00000000 0x0 0x00002000>; /* configuration space */
                        reg-names = "regs", "config";
                        interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
                        interrupt-names = "pme", "aer";
                        fsl,pcie-scfg = <&scfg 1>;
                        #address-cells = <3>;
                        #size-cells = <2>;
                        device_type = "pci";
                        num-lanes = <4>;
                        bus-range = <0x0 0xff>;
                        ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */
                                  0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
                        msi-parent = <&msi>;
                        #interrupt-cells = <1>;
                        interrupt-map-mask = <0 0 0 7>;
                        interrupt-map = <0000 0 0 1 &gic GIC_SPI 92  IRQ_TYPE_LEVEL_HIGH>,
                                        <0000 0 0 2 &gic GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
                                        <0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
                                        <0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
                };

 

In reg property, why does configuration space set 0x40 or 0x48? what's mean of the address of 0x40 or 0x48?

Please help! 

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