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Critical inconsistency with S32K144 ADC_SC1x register between CPU specification and actual value

Question asked by Justin Sheng on Oct 31, 2017
Latest reply on Nov 2, 2017 by Petr Stancik

There is a critical inconsistency identified between ADC specification and actual register value for ADC_SC1x.


Actual value in S32DS:

ADCH field only has 5 bits available and setting 0x1F disables it.Actual register value

These are the register values in memory window:

 Memory window


CPU specification:

ADCH field has 6 bits available and setting 0x3F disables it, while 0x1F is a reserved value.

CPU spec for ADC_SC1x

ADCH field description in spec

ADCH field description in spec


Hope NXP can clarify this issue. Which one is correct?